Lines Matching refs:clk_mgt
453 struct clk_mgt {
470 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
1257 val = readl(prcmu_base + clk_mgt[clock].offset);
1259 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1261 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1264 writel(val, prcmu_base + clk_mgt[clock].offset);
1440 val = readl(prcmu_base + clk_mgt[clock].offset);
1443 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1448 val |= clk_mgt[clock].pllsw;
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1601 val = readl(prcmu_base + clk_mgt[clock].offset);
1602 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1603 clk_mgt[clock].branch);
1606 if (clk_mgt[clock].clk38div) {
1761 val = readl(prcmu_base + clk_mgt[clock].offset);
1762 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1763 clk_mgt[clock].branch);
1766 if (clk_mgt[clock].clk38div) {
1789 writel(val, prcmu_base + clk_mgt[clock].offset);