Lines Matching defs:rate

1399 	u64 rate;
1406 rate = src_rate;
1407 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1427 (void)do_div(rate, div);
1429 return (unsigned long)rate;
1438 unsigned long rate = ROOT_CLOCK_RATE;
1444 rate /= 2;
1445 return rate;
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1462 u64 r = (rate * 10);
1469 return rate / val;
1477 unsigned long rate;
1484 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1488 rate /= 2;
1493 rate /= r;
1496 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1499 return rate;
1582 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1586 div = (src_rate / rate);
1589 if (rate < (src_rate / div))
1594 static long round_clock_rate(u8 clock, unsigned long rate)
1604 div = clock_divider(src_rate, rate);
1616 if (r <= rate)
1639 static long round_armss_rate(unsigned long rate)
1657 if (rate <= freq)
1668 static long round_plldsi_rate(unsigned long rate)
1676 rem = rate;
1681 d = (r * rate);
1692 if (rate < d) {
1697 if ((rate - d) < rem) {
1698 rem = (rate - d);
1705 static long round_dsiclk_rate(unsigned long rate)
1713 div = clock_divider(src_rate, rate);
1719 static long round_dsiescclk_rate(unsigned long rate)
1726 div = clock_divider(src_rate, rate);
1732 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1735 return round_clock_rate(clock, rate);
1737 return round_armss_rate(rate);
1739 return round_plldsi_rate(rate);
1741 return round_dsiclk_rate(rate);
1743 return round_dsiescclk_rate(rate);
1748 static void set_clock_rate(u8 clock, unsigned long rate)
1764 div = clock_divider(src_rate, rate);
1779 if (r <= rate) {
1797 static int set_armss_rate(unsigned long rate)
1816 if (rate == freq)
1820 if (rate != freq)
1828 static int set_plldsi_rate(unsigned long rate)
1836 rem = rate;
1842 d = (r * rate);
1853 if (rate < hwrate) {
1859 if ((rate - hwrate) < rem) {
1860 rem = (rate - hwrate);
1874 static void set_dsiclk_rate(u8 n, unsigned long rate)
1880 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1892 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1897 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1904 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1907 set_clock_rate(clock, rate);
1909 return set_armss_rate(rate);
1911 return set_plldsi_rate(rate);
1913 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1915 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);