Lines Matching refs:str
58 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
61 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
64 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
67 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
70 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
73 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
76 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
79 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
82 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
85 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
88 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
91 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
94 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
97 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
104 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
107 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
110 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
113 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
116 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
119 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
127 str r1, [r4, r5]
150 str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
151 str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
154 str r1, [r0, #EMIF_SDRAM_TIMING_1]
155 str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
158 str r1, [r0, #EMIF_SDRAM_TIMING_2]
159 str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
162 str r1, [r0, #EMIF_SDRAM_TIMING_3]
163 str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
166 str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
167 str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
170 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
173 str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
176 str r1, [r0, #EMIF_COS_CONFIG]
179 str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
182 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
185 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
188 str r1, [r0, #EMIF_OCP_CONFIG]
195 str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
198 str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
201 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
204 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
207 str r1, [r0, #EMIF_DLL_CALIB_CTRL]
210 str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
213 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
224 str r1, [r4, r5]
237 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
265 str r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
305 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
333 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
335 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
361 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]