Lines Matching defs:timing
368 dev_err(emc->dev, "failed to update timing: %d\n", err);
399 struct emc_timing *timing = NULL;
404 timing = &emc->timings[i];
409 if (!timing) {
410 dev_err(emc->dev, "no timing for rate %lu\n", rate);
414 return timing;
417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
423 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) {
434 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) {
445 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) {
484 struct emc_timing *timing = emc_find_timing(emc, rate);
497 if (!timing || emc->bad_state)
500 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
501 __func__, timing->rate, rate);
516 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
518 else if (timing->emc_mode_1 & 0x1)
523 emc->dll_on = !!(timing->emc_mode_1 & 0x1);
525 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
560 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
574 if (timing->emc_auto_cal_interval) {
576 val ^= timing->data[74];
595 for (i = 0; i < ARRAY_SIZE(timing->data); i++) {
598 writel_relaxed(timing->data[i],
602 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
613 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK;
617 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
633 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK;
662 writel_relaxed(timing->emc_mode_1,
675 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
679 if (qrst_used || timing->emc_cfg_periodic_qrst != val) {
680 if (timing->emc_cfg_periodic_qrst)
696 if (timing->emc_mode_1 != emc->emc_mode_1)
697 writel_relaxed(timing->emc_mode_1,
700 if (timing->emc_mode_2 != emc->emc_mode_2)
701 writel_relaxed(timing->emc_mode_2,
704 if (timing->emc_mode_reset != emc->emc_mode_reset ||
706 val = timing->emc_mode_reset;
716 if (timing->emc_mode_2 != emc->emc_mode_2)
717 writel_relaxed(timing->emc_mode_2,
720 if (timing->emc_mode_1 != emc->emc_mode_1)
721 writel_relaxed(timing->emc_mode_1,
725 emc->emc_mode_1 = timing->emc_mode_1;
726 emc->emc_mode_2 = timing->emc_mode_2;
727 emc->emc_mode_reset = timing->emc_mode_reset;
754 struct emc_timing *timing = emc_find_timing(emc, rate);
774 writel_relaxed(timing->emc_auto_cal_interval,
778 if (timing->emc_cfg_dyn_self_ref) {
785 writel_relaxed(timing->emc_zcal_cnt_long,
791 /* update restored timing */
807 dev_err(emc->dev, "timing configuration can't be reverted\n");
848 struct emc_timing *timing,
856 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
861 timing->rate = value;
864 timing->data,
868 "timing %pOF: failed to read emc timing data: %d\n",
874 timing->prop = of_property_read_bool(node, dtprop);
877 err = of_property_read_u32(node, dtprop, &timing->prop); \
880 "timing %pOFn: failed to read " #prop ": %d\n", \
896 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
929 "emc/mc timing rate mismatch: %lu %lu\n",
942 struct emc_timing *timing;
952 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
958 timing = emc->timings;
961 err = load_one_timing_from_dt(emc, timing++, child);
968 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
1056 struct emc_timing *timing = NULL;
1076 timing = &emc->timings[i];
1080 if (!timing) {
1081 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1086 return timing->rate;