Lines Matching defs:emc
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
357 static int emc_seq_update_timing(struct tegra_emc *emc)
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val,
368 dev_err(emc->dev, "failed to update timing: %d\n", err);
377 struct tegra_emc *emc = data;
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
387 dev_err_ratelimited(emc->dev,
391 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
396 static struct emc_timing *emc_find_timing(struct tegra_emc *emc,
402 for (i = 0; i < emc->num_timings; i++) {
403 if (emc->timings[i].rate >= rate) {
404 timing = &emc->timings[i];
410 dev_err(emc->dev, "no timing for rate %lu\n", rate);
417 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing,
424 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2);
428 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
435 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3);
439 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
446 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL);
450 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
460 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate)
462 struct tegra_mc *mc = emc->mc;
476 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same);
482 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
484 struct emc_timing *timing = emc_find_timing(emc, rate);
497 if (!timing || emc->bad_state)
500 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
503 emc->bad_state = true;
505 err = emc_prepare_mc_clk_cfg(emc, rate);
507 dev_err(emc->dev, "mc clock preparation failed: %d\n", err);
511 emc->vref_cal_toggle = false;
512 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
513 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG);
514 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
516 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1))
523 emc->dll_on = !!(timing->emc_mode_1 & 0x1);
525 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL))
526 emc->zcal_long = true;
528 emc->zcal_long = false;
530 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
533 dram_num = tegra_mc_get_emem_device_count(emc->mc);
536 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) {
537 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE;
538 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
544 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ);
550 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ);
551 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
554 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK)
555 mc_writel(emc->mc,
556 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK,
560 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) {
566 err = emc_seq_update_timing(emc);
575 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL);
579 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
582 emc->regs + EMC_AUTO_CAL_STATUS, val,
585 dev_err(emc->dev,
590 emc->vref_cal_toggle = true;
599 emc->regs + emc_timing_registers[i]);
602 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate);
610 if (emc->zcal_long)
621 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
625 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL);
644 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE);
649 emc->regs + EMC_DBG);
650 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST,
651 emc->regs + EMC_CFG);
652 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
657 emc->regs + EMC_REFCTRL);
663 emc->regs + EMC_EMRS);
667 emc->regs + EMC_SELF_REF);
671 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
674 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG);
675 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL);
678 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST);
681 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST;
683 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST;
685 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
687 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
692 emc->regs + EMC_SELF_REF);
696 if (timing->emc_mode_1 != emc->emc_mode_1)
698 emc->regs + EMC_EMRS);
700 if (timing->emc_mode_2 != emc->emc_mode_2)
702 emc->regs + EMC_EMRS);
704 if (timing->emc_mode_reset != emc->emc_mode_reset ||
713 writel_relaxed(val, emc->regs + EMC_MRS);
716 if (timing->emc_mode_2 != emc->emc_mode_2)
718 emc->regs + EMC_MRW);
720 if (timing->emc_mode_1 != emc->emc_mode_1)
722 emc->regs + EMC_MRW);
725 emc->emc_mode_1 = timing->emc_mode_1;
726 emc->emc_mode_2 = timing->emc_mode_2;
727 emc->emc_mode_reset = timing->emc_mode_reset;
730 if (emc->zcal_long) {
732 emc->regs + EMC_ZQ_CAL);
736 emc->regs + EMC_ZQ_CAL);
740 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE);
746 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE);
751 static int emc_complete_timing_change(struct tegra_emc *emc,
754 struct emc_timing *timing = emc_find_timing(emc, rate);
759 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
763 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
768 dram_num = tegra_mc_get_emem_device_count(emc->mc);
770 emc->regs + EMC_REFCTRL);
773 if (emc->vref_cal_toggle)
775 emc->regs + EMC_AUTO_CAL_INTERVAL);
779 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE;
780 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
784 if (emc->zcal_long)
786 emc->regs + EMC_ZCAL_WAIT_CNT);
792 err = emc_seq_update_timing(emc);
794 emc->bad_state = false;
797 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE);
802 static int emc_unprepare_timing_change(struct tegra_emc *emc,
805 if (!emc->bad_state) {
807 dev_err(emc->dev, "timing configuration can't be reverted\n");
808 emc->bad_state = true;
817 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
827 disable_irq(emc->irq);
828 err = emc_prepare_timing_change(emc, cnd->new_rate);
829 enable_irq(emc->irq);
833 err = emc_unprepare_timing_change(emc, cnd->old_rate);
837 err = emc_complete_timing_change(emc, cnd->new_rate);
847 static int load_one_timing_from_dt(struct tegra_emc *emc,
856 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
863 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
867 dev_err(emc->dev,
868 "timing %pOF: failed to read emc timing data: %d\n",
879 dev_err(emc->dev, \
885 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
886 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1")
887 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2")
888 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset")
889 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
890 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref")
891 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst")
896 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate);
915 static int emc_check_mc_timings(struct tegra_emc *emc)
917 struct tegra_mc *mc = emc->mc;
920 if (emc->num_timings != mc->num_timings) {
921 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
922 emc->num_timings, mc->num_timings);
927 if (emc->timings[i].rate != mc->timings[i].rate) {
928 dev_err(emc->dev,
929 "emc/mc timing rate mismatch: %lu %lu\n",
930 emc->timings[i].rate, mc->timings[i].rate);
938 static int emc_load_timings_from_dt(struct tegra_emc *emc,
948 dev_err(emc->dev, "no memory timings in: %pOF\n", node);
952 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
954 if (!emc->timings)
957 emc->num_timings = child_count;
958 timing = emc->timings;
961 err = load_one_timing_from_dt(emc, timing++, child);
968 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
971 err = emc_check_mc_timings(emc);
975 dev_info(emc->dev,
977 emc->num_timings,
979 emc->timings[0].rate / 1000000,
980 emc->timings[emc->num_timings - 1].rate / 1000000);
1007 static int emc_setup_hw(struct tegra_emc *emc)
1013 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
1016 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
1034 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
1037 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
1038 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
1041 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
1046 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1057 struct tegra_emc *emc = arg;
1060 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
1062 for (i = 0; i < emc->num_timings; i++) {
1063 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
1066 if (emc->timings[i].rate > max_rate) {
1069 if (emc->timings[i].rate < min_rate)
1073 if (emc->timings[i].rate < min_rate)
1076 timing = &emc->timings[i];
1081 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
1095 * /sys/kernel/debug/emc
1114 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
1118 for (i = 0; i < emc->num_timings; i++)
1119 if (rate == emc->timings[i].rate)
1127 struct tegra_emc *emc = s->private;
1131 for (i = 0; i < emc->num_timings; i++) {
1132 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
1157 struct tegra_emc *emc = data;
1159 *rate = emc->debugfs.min_rate;
1166 struct tegra_emc *emc = data;
1169 if (!tegra_emc_validate_rate(emc, rate))
1172 err = clk_set_min_rate(emc->clk, rate);
1176 emc->debugfs.min_rate = rate;
1187 struct tegra_emc *emc = data;
1189 *rate = emc->debugfs.max_rate;
1196 struct tegra_emc *emc = data;
1199 if (!tegra_emc_validate_rate(emc, rate))
1202 err = clk_set_max_rate(emc->clk, rate);
1206 emc->debugfs.max_rate = rate;
1215 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
1217 struct device *dev = emc->dev;
1221 emc->debugfs.min_rate = ULONG_MAX;
1222 emc->debugfs.max_rate = 0;
1224 for (i = 0; i < emc->num_timings; i++) {
1225 if (emc->timings[i].rate < emc->debugfs.min_rate)
1226 emc->debugfs.min_rate = emc->timings[i].rate;
1228 if (emc->timings[i].rate > emc->debugfs.max_rate)
1229 emc->debugfs.max_rate = emc->timings[i].rate;
1232 if (!emc->num_timings) {
1233 emc->debugfs.min_rate = clk_get_rate(emc->clk);
1234 emc->debugfs.max_rate = emc->debugfs.min_rate;
1237 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
1238 emc->debugfs.max_rate);
1241 emc->debugfs.min_rate, emc->debugfs.max_rate,
1242 emc->clk);
1245 emc->debugfs.root = debugfs_create_dir("emc", NULL);
1246 if (!emc->debugfs.root) {
1247 dev_err(emc->dev, "failed to create debugfs directory\n");
1251 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
1252 emc, &tegra_emc_debug_available_rates_fops);
1253 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
1254 emc, &tegra_emc_debug_min_rate_fops);
1255 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
1256 emc, &tegra_emc_debug_max_rate_fops);
1263 struct tegra_emc *emc;
1287 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1288 if (!emc) {
1293 emc->mc = platform_get_drvdata(mc);
1294 if (!emc->mc)
1297 emc->clk_nb.notifier_call = emc_clk_change_notify;
1298 emc->dev = &pdev->dev;
1300 err = emc_load_timings_from_dt(emc, np);
1305 emc->regs = devm_platform_ioremap_resource(pdev, 0);
1306 if (IS_ERR(emc->regs))
1307 return PTR_ERR(emc->regs);
1309 err = emc_setup_hw(emc);
1318 emc->irq = err;
1320 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
1321 dev_name(&pdev->dev), emc);
1327 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1329 emc->clk = devm_clk_get(&pdev->dev, "emc");
1330 if (IS_ERR(emc->clk)) {
1331 err = PTR_ERR(emc->clk);
1332 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
1336 err = clk_notifier_register(emc->clk, &emc->clk_nb);
1343 platform_set_drvdata(pdev, emc);
1344 tegra_emc_debugfs_init(emc);
1356 struct tegra_emc *emc = dev_get_drvdata(dev);
1360 err = clk_rate_exclusive_get(emc->clk);
1362 dev_err(emc->dev, "failed to acquire clk: %d\n", err);
1367 if (WARN(emc->bad_state, "hardware in a bad state\n"))
1370 emc->bad_state = true;
1377 struct tegra_emc *emc = dev_get_drvdata(dev);
1379 emc_setup_hw(emc);
1380 emc->bad_state = false;
1382 clk_rate_exclusive_put(emc->clk);
1393 { .compatible = "nvidia,tegra30-emc", },
1400 .name = "tegra30-emc",