Lines Matching refs:next
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
105 next->ptfv_list[w])) / \
106 (next->ptfv_list[w] + 1); \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
120 struct tegra210_emc_timing *next = emc->next;
122 u32 next_timing_rate_mhz = next->rate / 1000;
168 tdel = next->current_dram_clktree[C0D0U0] -
169 __MOVAVG_AC(next, C0D0U0);
174 next->tree_margin)
175 next->current_dram_clktree[C0D0U0] =
176 __MOVAVG_AC(next, C0D0U0);
193 tdel = next->current_dram_clktree[C0D0U1] -
194 __MOVAVG_AC(next, C0D0U1);
201 next->tree_margin)
202 next->current_dram_clktree[C0D0U1] =
203 __MOVAVG_AC(next, C0D0U1);
221 tdel = next->current_dram_clktree[C1D0U0] -
222 __MOVAVG_AC(next, C1D0U0);
229 next->tree_margin)
230 next->current_dram_clktree[C1D0U0] =
231 __MOVAVG_AC(next, C1D0U0);
248 tdel = next->current_dram_clktree[C1D0U1] -
249 __MOVAVG_AC(next, C1D0U1);
256 next->tree_margin)
257 next->current_dram_clktree[C1D0U1] =
258 __MOVAVG_AC(next, C1D0U1);
303 tdel = next->current_dram_clktree[C0D1U0] -
304 __MOVAVG_AC(next, C0D1U0);
311 next->tree_margin)
312 next->current_dram_clktree[C0D1U0] =
313 __MOVAVG_AC(next, C0D1U0);
330 tdel = next->current_dram_clktree[C0D1U1] -
331 __MOVAVG_AC(next, C0D1U1);
338 next->tree_margin)
339 next->current_dram_clktree[C0D1U1] =
340 __MOVAVG_AC(next, C0D1U1);
358 tdel = next->current_dram_clktree[C1D1U0] -
359 __MOVAVG_AC(next, C1D1U0);
366 next->tree_margin)
367 next->current_dram_clktree[C1D1U0] =
368 __MOVAVG_AC(next, C1D1U0);
385 tdel = next->current_dram_clktree[C1D1U1] -
386 __MOVAVG_AC(next, C1D1U1);
393 next->tree_margin)
394 next->current_dram_clktree[C1D1U1] =
395 __MOVAVG_AC(next, C1D1U1);
405 struct tegra210_emc_timing *next)
411 u32 i, adel = 0, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX];
418 if (!next->periodic_training)
423 (next->ptfv_list[PTFV_CONFIG_CTRL_INDEX] &
430 __COPY_EMA(next, last, C0D0U0);
431 __COPY_EMA(next, last, C0D0U1);
432 __COPY_EMA(next, last, C1D0U0);
433 __COPY_EMA(next, last, C1D0U1);
434 __COPY_EMA(next, last, C0D1U0);
435 __COPY_EMA(next, last, C0D1U1);
436 __COPY_EMA(next, last, C1D1U0);
437 __COPY_EMA(next, last, C1D1U1);
440 __MOVAVG(next, C0D0U0) = 0;
441 __MOVAVG(next, C0D0U1) = 0;
442 __MOVAVG(next, C1D0U0) = 0;
443 __MOVAVG(next, C1D0U1) = 0;
444 __MOVAVG(next, C0D1U0) = 0;
445 __MOVAVG(next, C0D1U1) = 0;
446 __MOVAVG(next, C1D1U0) = 0;
447 __MOVAVG(next, C1D1U1) = 0;
454 * Generate next sample of data.
607 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next;
612 u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4];
636 if ((next->burst_regs[EMC_ZCAL_INTERVAL_INDEX] != 0 &&
642 opt_dll_mode = tegra210_emc_get_dll_state(next);
644 if ((next->burst_regs[EMC_FBIO_CFG5_INDEX] & BIT(25)) &&
652 dst_clk_period = 1000000000 / next->rate;
665 emc_cfg = next->burst_regs[EMC_CFG_INDEX];
668 emc_sel_dpd_ctrl = next->emc_sel_dpd_ctrl;
680 emc_dbg(emc, INFO, "DLL clksrc: 0x%08x\n", next->dll_clk_src);
681 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate,
682 next->rate);
683 emc_dbg(emc, INFO, "last period: %u, next period: %u\n",
708 emc_auto_cal_config = next->emc_auto_cal_config;
724 if (next->periodic_training) {
725 tegra210_emc_reset_dram_clktree_values(next);
743 next);
744 value = (value * 128 * next->rate / 1000) / 1000000;
746 if (next->periodic_training && value > next->tree_margin)
756 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp &
761 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
765 ((next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
770 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
773 (next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
793 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
797 ((next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
800 next->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
827 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] &
844 emc_writel(emc, next->emc_auto_cal_config2, EMC_AUTO_CAL_CONFIG2);
845 emc_writel(emc, next->emc_auto_cal_config3, EMC_AUTO_CAL_CONFIG3);
846 emc_writel(emc, next->emc_auto_cal_config4, EMC_AUTO_CAL_CONFIG4);
847 emc_writel(emc, next->emc_auto_cal_config5, EMC_AUTO_CAL_CONFIG5);
848 emc_writel(emc, next->emc_auto_cal_config6, EMC_AUTO_CAL_CONFIG6);
849 emc_writel(emc, next->emc_auto_cal_config7, EMC_AUTO_CAL_CONFIG7);
850 emc_writel(emc, next->emc_auto_cal_config8, EMC_AUTO_CAL_CONFIG8);
866 emc_writel(emc, next->emc_cfg_2, EMC_CFG_2);
877 zq_wait_long = max(next->min_mrs_wait,
930 next->burst_regs[EMC_RP_INDEX]);
985 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x80;
986 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0x00;
988 mr13_flip_fspwr = (next->emc_mrw3 & 0xffffff3f) | 0x40;
989 mr13_flip_fspop = (next->emc_mrw3 & 0xffffff3f) | 0xc0;
994 emc_writel(emc, next->emc_mrw, EMC_MRW);
995 emc_writel(emc, next->emc_mrw2, EMC_MRW2);
1005 for (i = 0; i < next->num_burst; i++) {
1012 value = next->burst_regs[i];
1073 tegra210_emc_adjust_timing(emc, next);
1077 (next->run_clocks & EMC_MRW_MRW_OP_MASK);
1084 for (i = 0; i < next->num_burst_per_ch; i++) {
1109 next->burst_reg_per_ch[i], burst[i].offset);
1111 next->burst_reg_per_ch[i],
1118 for (i = 0; i < next->vref_num; i++) {
1129 next->vref_perch_regs[i], vref[i].offset);
1130 emc_channel_writel(emc, vref[i].bank, next->vref_perch_regs[i],
1137 for (i = 0; i < next->num_trim; i++) {
1154 value = tegra210_emc_compensate(next, offsets[i]);
1162 next->trim_regs[i], offsets[i]);
1163 emc_writel(emc, next->trim_regs[i], offsets[i]);
1170 for (i = 0; i < next->num_trim_per_ch; i++) {
1194 value = tegra210_emc_compensate(next, offset);
1202 next->trim_perch_regs[i], offset);
1204 next->trim_perch_regs[i], offset);
1210 for (i = 0; i < next->num_mc_regs; i++) {
1212 u32 *values = next->burst_mc_regs;
1220 if (next->rate < last->rate) {
1225 for (i = 0; i < next->num_up_down; i++) {
1227 next->la_scale_regs[i], la[i]);
1228 mc_writel(emc->mc, next->la_scale_regs[i], la[i]);
1241 value = next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX];
1271 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &
1275 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &
1282 (next->burst_regs[EMC_MRW7_INDEX] &
1287 (next->burst_regs[EMC_MRW15_INDEX] &
1415 div_o3(1000 * next->dram_timings[T_PDEX],
1422 emc_dbg(emc, INFO, "next->dram_timings[T_PDEX] = %u\n",
1423 next->dram_timings[T_PDEX]);
1428 delay = div_o3(1000 * next->dram_timings[T_PDEX],
1508 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0);
1511 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);
1514 ccfifo_writel(emc, next->emc_emrs &
1516 ccfifo_writel(emc, next->emc_emrs2 &
1518 ccfifo_writel(emc, next->emc_mrs |
1577 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX],
1606 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
1610 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &
1627 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
1632 next->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
1664 if (next->rate > last->rate) {
1665 for (i = 0; i < next->num_up_down; i++)
1666 mc_writel(emc->mc, next->la_scale_regs[i],
1680 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],
1682 emc_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
1693 emc_writel(emc, next->burst_regs[EMC_MRS_WAIT_CNT_INDEX],
1696 emc_writel(emc, next->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX],
1708 emc_writel(emc, next->burst_regs[EMC_CFG_INDEX], EMC_CFG);
1710 emc_writel(emc, next->emc_fdpd_ctrl_cmd_no_ramp,
1712 emc_writel(emc, next->emc_sel_dpd_ctrl, EMC_SEL_DPD_CTRL);
1722 next->burst_regs[EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX],
1753 if (next->burst_regs[EMC_CFG_DIG_DLL_INDEX] & EMC_CFG_DIG_DLL_CFG_DLL_EN) {
1765 emc_writel(emc, next->emc_auto_cal_config, EMC_AUTO_CAL_CONFIG);