Lines Matching refs:ccfifo_writel
864 ccfifo_writel(emc, 1, EMC_SELF_REF, 0);
1264 ccfifo_writel(emc, 0x101, EMC_SELF_REF, 0);
1266 ccfifo_writel(emc, 0x1, EMC_SELF_REF, 0);
1270 ccfifo_writel(emc, mr13_flip_fspwr ^ 0x40, EMC_MRW3, 0);
1271 ccfifo_writel(emc, (next->burst_regs[EMC_MRW6_INDEX] &
1275 ccfifo_writel(emc, (next->burst_regs[EMC_MRW14_INDEX] &
1281 ccfifo_writel(emc,
1286 ccfifo_writel(emc,
1295 ccfifo_writel(emc,
1300 ccfifo_writel(emc,
1305 ccfifo_writel(emc,
1314 ccfifo_writel(emc, mr13_flip_fspop | 0x8, EMC_MRW3, value);
1315 ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period);
1327 ccfifo_writel(emc, emc_pin & ~(EMC_PIN_PIN_CKE_PER_DEV |
1359 ccfifo_writel(emc, 0x0, EMC_CFG_SYNC, delay);
1362 ccfifo_writel(emc, value, EMC_DBG, 0);
1373 ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE, 0);
1375 ccfifo_writel(emc, value, EMC_DBG, 0);
1384 ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
1400 ccfifo_writel(emc, value, EMC_PIN, 0);
1433 ccfifo_writel(emc,
1439 ccfifo_writel(emc, value, EMC_MRW3, delay);
1440 ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
1441 ccfifo_writel(emc, 0, EMC_REF, 0);
1442 ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
1448 ccfifo_writel(emc,
1453 ccfifo_writel(emc, 2UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
1457 ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
1462 ccfifo_writel(emc, value, EMC_MRW3, 0);
1463 ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
1464 ccfifo_writel(emc, 0, EMC_REF, 0);
1466 ccfifo_writel(emc, 1UL << EMC_ZQ_CAL_DEV_SEL_SHIFT |
1471 ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_CAL_CMD,
1475 ccfifo_writel(emc, value, EMC_MRW3, delay);
1476 ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
1477 ccfifo_writel(emc, 0, EMC_REF, 0);
1479 ccfifo_writel(emc, EMC_ZQ_CAL_ZQ_LATCH_CMD, EMC_ZQ_CAL,
1485 ccfifo_writel(emc, 0, 0, 10);
1499 ccfifo_writel(emc, 0, EMC_SELF_REF, 0);
1508 ccfifo_writel(emc, next->emc_mrw2, EMC_MRW2, 0);
1509 ccfifo_writel(emc, next->emc_mrw, EMC_MRW, 0);
1511 ccfifo_writel(emc, next->emc_mrw4, EMC_MRW4, 0);
1514 ccfifo_writel(emc, next->emc_emrs &
1516 ccfifo_writel(emc, next->emc_emrs2 &
1518 ccfifo_writel(emc, next->emc_mrs |
1536 ccfifo_writel(emc, value, EMC_MRS_WAIT_CNT2, 0);
1539 ccfifo_writel(emc, 2 << EMC_MRW_MRW_DEV_SELECTN_SHIFT |
1550 ccfifo_writel(emc, value, EMC_MRW, 0);
1555 ccfifo_writel(emc, value |
1563 ccfifo_writel(emc, value, EMC_ZQ_CAL, 0);
1576 ccfifo_writel(emc,
1589 ccfifo_writel(emc, 0, EMC_REF, 0);
1592 ccfifo_writel(emc, 1, EMC_ISSUE_QRST, 0);
1593 ccfifo_writel(emc, 0, EMC_ISSUE_QRST, 2);
1603 ccfifo_writel(emc, emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE,
1606 ccfifo_writel(emc, next->burst_regs[EMC_ZCAL_INTERVAL_INDEX],
1610 ccfifo_writel(emc, next->burst_regs[EMC_CFG_INDEX] &
1613 ccfifo_writel(emc, emc_dbg, EMC_DBG, 0);
1622 ccfifo_writel(emc, emc_cfg_pipe_clk, EMC_CFG_PIPE_CLK, 0);