Lines Matching defs:last
119 struct tegra210_emc_timing *last = emc->last;
121 u32 last_timing_rate_mhz = last->rate / 1000;
155 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
180 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
208 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
235 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
290 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
317 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
345 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
372 cval = tegra210_emc_actual_osc_clocks(last->run_clocks);
404 struct tegra210_emc_timing *last,
414 delay = tegra210_emc_actual_osc_clocks(last->run_clocks);
416 delay = 2 + (delay / last->rate);
422 if (last->periodic_training &&
430 __COPY_EMA(next, last, C0D0U0);
431 __COPY_EMA(next, last, C0D0U1);
432 __COPY_EMA(next, last, C1D0U0);
433 __COPY_EMA(next, last, C1D0U1);
434 __COPY_EMA(next, last, C0D1U0);
435 __COPY_EMA(next, last, C0D1U1);
436 __COPY_EMA(next, last, C1D1U0);
437 __COPY_EMA(next, last, C1D1U1);
493 struct tegra210_emc_timing *last = emc->last;
497 if (last->periodic_training) {
539 delay = tegra210_emc_actual_osc_clocks(last->run_clocks);
541 delay /= last->rate + 1;
550 last, last);
556 if (last->tree_margin < ((del * 128 * (last->rate / 1000)) / 1000000)) {
558 value = tegra210_emc_compensate(last, list[i]);
607 struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next;
626 /* XXX fake == last */
627 fake = tegra210_emc_find_timing(emc, last->rate * 1000UL);
633 if (last->burst_regs[EMC_ZCAL_WAIT_CNT_INDEX] & BIT(31))
637 last->burst_regs[EMC_ZCAL_INTERVAL_INDEX] == 0) ||
651 src_clk_period = 1000000000 / last->rate;
681 emc_dbg(emc, INFO, "last rate: %u, next rate %u\n", last->rate,
683 emc_dbg(emc, INFO, "last period: %u, next period: %u\n",
739 delay = 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks);
740 udelay((delay / last->rate) + 2);
763 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
767 (last->burst_regs[EMC_PMACRO_BG_BIAS_CTRL_0_INDEX] &
778 emc_writel(emc, last->burst_regs
784 emc_writel(emc, last->burst_regs
791 if ((((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
795 (((last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX] &
802 last->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX];
924 tRPST = (last->emc_mrw & 0x80) >> 7;
932 if (last->burst_regs[EMC_RP_INDEX] < tRTM) {
933 if (tRTM > (last->burst_regs[EMC_R2P_INDEX] +
934 last->burst_regs[EMC_RP_INDEX])) {
935 R2P_war = tRTM - last->burst_regs[EMC_RP_INDEX];
936 RP_war = last->burst_regs[EMC_RP_INDEX];
937 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX];
941 last->burst_regs[EMC_RP_INDEX] - 63;
949 R2P_war = last->burst_regs[EMC_R2P_INDEX];
950 RP_war = last->burst_regs[EMC_RP_INDEX];
951 TRPab_war = last->burst_regs[EMC_TRPAB_INDEX];
955 W2P_war = last->burst_regs[EMC_W2P_INDEX]
964 W2P_war = last->burst_regs[
968 if ((last->burst_regs[EMC_W2P_INDEX] ^ W2P_war) ||
969 (last->burst_regs[EMC_R2P_INDEX] ^ R2P_war) ||
970 (last->burst_regs[EMC_RP_INDEX] ^ RP_war) ||
971 (last->burst_regs[EMC_TRPAB_INDEX] ^ TRPab_war)) {
1220 if (next->rate < last->rate) {
1273 (last->burst_regs[EMC_MRW6_INDEX] &
1277 (last->burst_regs[EMC_MRW14_INDEX] &
1284 (last->burst_regs[EMC_MRW7_INDEX] &
1289 (last->burst_regs[EMC_MRW15_INDEX] &
1664 if (next->rate > last->rate) {