Lines Matching defs:emc
163 struct tegra_emc *emc = data;
167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
173 dev_err_ratelimited(emc->dev,
177 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
188 for (i = 0; i < emc->num_timings; i++) {
189 if (emc->timings[i].rate >= rate) {
190 timing = &emc->timings[i];
196 dev_err(emc->dev, "no timing for rate %lu\n", rate);
203 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
205 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
211 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
217 emc->regs + emc_timing_registers[i]);
220 readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
225 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
230 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
235 emc->regs + EMC_TIMING_CONTROL);
239 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
243 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
253 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
259 err = emc_prepare_timing_change(emc, cnd->new_rate);
263 err = emc_prepare_timing_change(emc, cnd->old_rate);
267 err = emc_complete_timing_change(emc, true);
271 err = emc_complete_timing_change(emc, false);
281 static int load_one_timing_from_dt(struct tegra_emc *emc,
288 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
289 dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
295 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
300 err = of_property_read_u32_array(node, "nvidia,emc-registers",
304 dev_err(emc->dev,
305 "timing %pOF: failed to read emc timing data: %d\n",
316 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
336 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
346 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
350 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
352 if (!emc->timings)
355 emc->num_timings = child_count;
356 timing = emc->timings;
359 err = load_one_timing_from_dt(emc, timing++, child);
366 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
369 dev_info(emc->dev,
371 emc->num_timings,
373 emc->timings[0].rate / 1000000,
374 emc->timings[emc->num_timings - 1].rate / 1000000);
391 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
392 np = of_find_node_by_name(np, "emc-tables")) {
408 static int emc_setup_hw(struct tegra_emc *emc)
413 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
421 dev_err(emc->dev,
428 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
431 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
432 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
435 emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
440 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
451 struct tegra_emc *emc = arg;
454 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
456 for (i = 0; i < emc->num_timings; i++) {
457 if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
460 if (emc->timings[i].rate > max_rate) {
463 if (emc->timings[i].rate < min_rate)
467 if (emc->timings[i].rate < min_rate)
470 timing = &emc->timings[i];
475 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
489 * /sys/kernel/debug/emc
508 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
512 for (i = 0; i < emc->num_timings; i++)
513 if (rate == emc->timings[i].rate)
521 struct tegra_emc *emc = s->private;
525 for (i = 0; i < emc->num_timings; i++) {
526 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
551 struct tegra_emc *emc = data;
553 *rate = emc->debugfs.min_rate;
560 struct tegra_emc *emc = data;
563 if (!tegra_emc_validate_rate(emc, rate))
566 err = clk_set_min_rate(emc->clk, rate);
570 emc->debugfs.min_rate = rate;
581 struct tegra_emc *emc = data;
583 *rate = emc->debugfs.max_rate;
590 struct tegra_emc *emc = data;
593 if (!tegra_emc_validate_rate(emc, rate))
596 err = clk_set_max_rate(emc->clk, rate);
600 emc->debugfs.max_rate = rate;
609 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
611 struct device *dev = emc->dev;
615 emc->debugfs.min_rate = ULONG_MAX;
616 emc->debugfs.max_rate = 0;
618 for (i = 0; i < emc->num_timings; i++) {
619 if (emc->timings[i].rate < emc->debugfs.min_rate)
620 emc->debugfs.min_rate = emc->timings[i].rate;
622 if (emc->timings[i].rate > emc->debugfs.max_rate)
623 emc->debugfs.max_rate = emc->timings[i].rate;
626 if (!emc->num_timings) {
627 emc->debugfs.min_rate = clk_get_rate(emc->clk);
628 emc->debugfs.max_rate = emc->debugfs.min_rate;
631 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
632 emc->debugfs.max_rate);
635 emc->debugfs.min_rate, emc->debugfs.max_rate,
636 emc->clk);
639 emc->debugfs.root = debugfs_create_dir("emc", NULL);
640 if (!emc->debugfs.root) {
641 dev_err(emc->dev, "failed to create debugfs directory\n");
645 debugfs_create_file("available_rates", 0444, emc->debugfs.root,
646 emc, &tegra_emc_debug_available_rates_fops);
647 debugfs_create_file("min_rate", 0644, emc->debugfs.root,
648 emc, &tegra_emc_debug_min_rate_fops);
649 debugfs_create_file("max_rate", 0644, emc->debugfs.root,
650 emc, &tegra_emc_debug_max_rate_fops);
656 struct tegra_emc *emc;
678 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
679 if (!emc) {
684 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
685 emc->dev = &pdev->dev;
687 err = tegra_emc_load_timings_from_dt(emc, np);
693 emc->regs = devm_ioremap_resource(&pdev->dev, res);
694 if (IS_ERR(emc->regs))
695 return PTR_ERR(emc->regs);
697 err = emc_setup_hw(emc);
702 dev_name(&pdev->dev), emc);
708 tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
710 emc->clk = devm_clk_get(&pdev->dev, "emc");
711 if (IS_ERR(emc->clk)) {
712 err = PTR_ERR(emc->clk);
713 dev_err(&pdev->dev, "failed to get emc clock: %d\n", err);
717 err = clk_notifier_register(emc->clk, &emc->clk_nb);
724 platform_set_drvdata(pdev, emc);
725 tegra_emc_debugfs_init(emc);
736 { .compatible = "nvidia,tegra20-emc", },
743 .name = "tegra20-emc",