Lines Matching refs:x200
981 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
982 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
983 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
984 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
985 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
986 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
987 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
988 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
989 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
990 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
991 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
992 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
993 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
994 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
995 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
996 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
997 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
998 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
999 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1000 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1001 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),