Lines Matching refs:timing
509 dev_err(emc->dev, "timing update timed out\n");
547 struct emc_timing *timing = NULL;
552 timing = &emc->timings[i];
557 if (!timing) {
558 dev_err(emc->dev, "no timing for rate %lu\n", rate);
562 return timing;
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
576 if (!timing)
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
581 else if (timing->emc_mode_1 & 0x1)
613 if (!(timing->emc_bgbias_ctl0 &
633 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
639 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
658 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
660 writel(timing->emc_ctt_term_ctrl,
666 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
667 writel(timing->emc_burst_data[i],
670 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
673 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
679 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
680 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
683 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
684 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
687 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
688 val = timing->emc_auto_cal_config;
698 if (timing->emc_zcal_interval != 0 &&
702 val = (timing->emc_mrs_wait_cnt
708 val = timing->emc_mrs_wait_cnt
716 val = timing->emc_cfg_2;
722 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
745 if (timing->emc_mode_1 != last->emc_mode_1)
746 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
747 if (timing->emc_mode_2 != last->emc_mode_2)
748 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
750 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
752 val = timing->emc_mode_reset;
762 if (timing->emc_mode_2 != last->emc_mode_2)
763 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
764 if (timing->emc_mode_1 != last->emc_mode_1)
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
766 if (timing->emc_mode_4 != last->emc_mode_4)
767 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
771 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
796 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
800 if (!timing)
807 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
808 writel(timing->emc_auto_cal_interval,
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
813 writel(timing->emc_cfg, emc->regs + EMC_CFG);
816 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
820 timing->emc_bgbias_ctl0 &
822 val = timing->emc_bgbias_ctl0;
829 timing->emc_bgbias_ctl0) {
830 writel(timing->emc_bgbias_ctl0,
834 writel(timing->emc_auto_cal_interval,
838 /* Wait for timing to settle */
842 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
845 emc->last_timing = *timing;
851 struct emc_timing *timing)
856 timing->emc_burst_data[i] =
859 timing->emc_cfg = readl(emc->regs + EMC_CFG);
861 timing->emc_auto_cal_interval = 0;
862 timing->emc_zcal_cnt_long = 0;
863 timing->emc_mode_1 = 0;
864 timing->emc_mode_2 = 0;
865 timing->emc_mode_4 = 0;
866 timing->emc_mode_reset = 0;
883 struct emc_timing *timing,
891 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
896 timing->rate = value;
899 timing->emc_burst_data,
900 ARRAY_SIZE(timing->emc_burst_data));
903 "timing %pOFn: failed to read emc burst data: %d\n",
909 err = of_property_read_u32(node, dtprop, &timing->prop); \
911 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
958 struct emc_timing *timing;
962 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
970 timing = &emc->timings[i++];
972 err = load_one_timing_from_dt(emc, timing, child);
979 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,