Lines Matching refs:val
203 unsigned int val;
847 u32 val;
857 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
858 if (val) {
861 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
863 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
866 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
1045 u32 val;
1055 val = dmc->timings->tRFC / clk_period_ps;
1056 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1057 val = max(val, dmc->min_tck->tRFC);
1059 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1061 val = dmc->timings->tRRD / clk_period_ps;
1062 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1063 val = max(val, dmc->min_tck->tRRD);
1065 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1067 val = dmc->timings->tRPab / clk_period_ps;
1068 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1069 val = max(val, dmc->min_tck->tRPab);
1071 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1073 val = dmc->timings->tRCD / clk_period_ps;
1074 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1075 val = max(val, dmc->min_tck->tRCD);
1077 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1079 val = dmc->timings->tRC / clk_period_ps;
1080 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1081 val = max(val, dmc->min_tck->tRC);
1083 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1085 val = dmc->timings->tRAS / clk_period_ps;
1086 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1087 val = max(val, dmc->min_tck->tRAS);
1089 *reg_timing_row |= TIMING_VAL2REG(reg, val);
1092 val = dmc->timings->tWTR / clk_period_ps;
1093 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1094 val = max(val, dmc->min_tck->tWTR);
1096 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1098 val = dmc->timings->tWR / clk_period_ps;
1099 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1100 val = max(val, dmc->min_tck->tWR);
1102 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1104 val = dmc->timings->tRTP / clk_period_ps;
1105 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1106 val = max(val, dmc->min_tck->tRTP);
1108 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1110 val = dmc->timings->tW2W_C2C / clk_period_ps;
1111 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1112 val = max(val, dmc->min_tck->tW2W_C2C);
1114 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1116 val = dmc->timings->tR2R_C2C / clk_period_ps;
1117 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1118 val = max(val, dmc->min_tck->tR2R_C2C);
1120 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1122 val = dmc->timings->tWL / clk_period_ps;
1123 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1124 val = max(val, dmc->min_tck->tWL);
1126 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1128 val = dmc->timings->tDQSCK / clk_period_ps;
1129 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1130 val = max(val, dmc->min_tck->tDQSCK);
1132 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1134 val = dmc->timings->tRL / clk_period_ps;
1135 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1136 val = max(val, dmc->min_tck->tRL);
1138 *reg_timing_data |= TIMING_VAL2REG(reg, val);
1141 val = dmc->timings->tFAW / clk_period_ps;
1142 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1143 val = max(val, dmc->min_tck->tFAW);
1145 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1147 val = dmc->timings->tXSR / clk_period_ps;
1148 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1149 val = max(val, dmc->min_tck->tXSR);
1151 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1153 val = dmc->timings->tXP / clk_period_ps;
1154 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1155 val = max(val, dmc->min_tck->tXP);
1157 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1159 val = dmc->timings->tCKE / clk_period_ps;
1160 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1161 val = max(val, dmc->min_tck->tCKE);
1163 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1165 val = dmc->timings->tMRD / clk_period_ps;
1166 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1167 val = max(val, dmc->min_tck->tMRD);
1169 *reg_timing_power |= TIMING_VAL2REG(reg, val);
1386 unsigned int val;
1389 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1393 val |= 1UL;
1394 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);