Lines Matching refs:set
75 * set, otherwise it could crash.
89 * There is a set of different types, the values are from range 0 to 0x6f.
301 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
303 * @set: boolean variable passing set value
305 * Changes the register set, which holds timing parameters.
306 * There is two register sets: 0 and 1. The register set 0
308 * The bank register set 1 is used when the main PLL frequency is going to be
313 static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
322 if (set)
387 * It uses timing bank registers set 1.
417 * It uses timing bank registers set 0.
452 * @dmc: device for which it is going to be set
457 * voltage might be lower that currently set and still the system will be
478 * @dmc: device for which it is going to be set
504 * @dmc: device for which it is going to be set
525 * @target_rate: new frequency which is going to be set as a final
526 * @target_volt: new voltage which is going to be set as a final
574 * alternative clock source set as parent is stable.
578 * timings: set 0 and set 1. The set 0 is used when main clock source is
579 * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between
600 * Voltage is set at least to a level needed for this frequency,
684 * frequency and voltage change. In case of failure, does not set 'curr_rate'
960 dev_err(dev, "could not set event counter\n");
1002 * @dmc: device for which the frequency is going to be set
1003 * @bootloader_init_freq: initial frequency set by the bootloader in KHz
1030 * @dmc: device for which the frequency is going to be set
1176 * @dmc: device for which the frequency is going to be set
1256 * Get the needed clocks defined in DT device, enable and set the right parents.
1295 * Convert frequency to KHz values and set it for the governor.
1316 * Some bootloaders do not set clock routes correctly.
1368 dev_err(dmc->dev, "could not set event counter\n");