Lines Matching defs:target_rate
283 * @target_rate: requested frequency in KHz
289 unsigned long target_rate)
294 if (dmc->opp[i].freq_hz <= target_rate)
411 * @target_rate: target frequency of the DMC
420 unsigned long target_rate)
425 if (dmc->opp[idx].freq_hz <= target_rate)
505 * @target_rate: new frequency which is chosen to be final
510 unsigned long target_rate)
512 int idx = find_target_freq_idx(dmc, target_rate);
525 * @target_rate: new frequency which is going to be set as a final
535 unsigned long target_rate,
552 ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
568 * @target_rate: requested new frequency
589 unsigned long target_rate,
594 ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
616 exynos5_dram_change_timings(dmc, target_rate);
618 clk_set_rate(dmc->fout_bpll, target_rate);
647 * @target_rate: returned frequency which is the same or lower than
654 * frequency and voltage. It populates the values 'target_rate' and
659 unsigned long *target_rate,
668 *target_rate = dev_pm_opp_get_freq(opp);
691 unsigned long target_rate = 0;
695 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
701 if (target_rate == dmc->curr_rate)
706 ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
713 dmc->curr_rate = target_rate;
1263 unsigned long target_rate = 0;
1301 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,