Lines Matching defs:dmc
238 static int exynos5_counters_set_event(struct exynos5_dmc *dmc)
242 for (i = 0; i < dmc->num_counters; i++) {
243 if (!dmc->counter[i])
245 ret = devfreq_event_set_event(dmc->counter[i]);
252 static int exynos5_counters_enable_edev(struct exynos5_dmc *dmc)
256 for (i = 0; i < dmc->num_counters; i++) {
257 if (!dmc->counter[i])
259 ret = devfreq_event_enable_edev(dmc->counter[i]);
266 static int exynos5_counters_disable_edev(struct exynos5_dmc *dmc)
270 for (i = 0; i < dmc->num_counters; i++) {
271 if (!dmc->counter[i])
273 ret = devfreq_event_disable_edev(dmc->counter[i]);
282 * @dmc: device for which the information is checked
288 static int find_target_freq_idx(struct exynos5_dmc *dmc,
293 for (i = dmc->opp_count - 1; i >= 0; i--)
294 if (dmc->opp[i].freq_hz <= target_rate)
302 * @dmc: device for which the new settings is going to be applied
313 static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
318 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
327 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
334 * @dmc: DMC device for which the frequencies are used for OPP init
339 static int exynos5_init_freq_table(struct exynos5_dmc *dmc,
346 ret = dev_pm_opp_of_add_table(dmc->dev);
348 dev_err(dmc->dev, "Failed to get OPP table\n");
352 dmc->opp_count = dev_pm_opp_get_opp_count(dmc->dev);
354 dmc->opp = devm_kmalloc_array(dmc->dev, dmc->opp_count,
356 if (!dmc->opp)
359 idx = dmc->opp_count - 1;
360 for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) {
363 opp = dev_pm_opp_find_freq_floor(dmc->dev, &freq);
367 dmc->opp[idx - i].freq_hz = freq;
368 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp);
376 dev_pm_opp_of_remove_table(dmc->dev);
383 * @dmc: device for which the new settings is going to be applied
389 static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc)
392 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
394 writel(dmc->bypass_timing_row,
395 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
396 writel(dmc->bypass_timing_row,
397 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
398 writel(dmc->bypass_timing_data,
399 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
400 writel(dmc->bypass_timing_data,
401 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
402 writel(dmc->bypass_timing_power,
403 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
404 writel(dmc->bypass_timing_power,
405 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
410 * @dmc: device for which the new settings is going to be applied
419 static int exynos5_dram_change_timings(struct exynos5_dmc *dmc,
424 for (idx = dmc->opp_count - 1; idx >= 0; idx--)
425 if (dmc->opp[idx].freq_hz <= target_rate)
432 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
434 writel(dmc->timing_row[idx],
435 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
436 writel(dmc->timing_row[idx],
437 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
438 writel(dmc->timing_data[idx],
439 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
440 writel(dmc->timing_data[idx],
441 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
442 writel(dmc->timing_power[idx],
443 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
444 writel(dmc->timing_power[idx],
445 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
452 * @dmc: device for which it is going to be set
460 static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc,
465 if (dmc->curr_volt <= target_volt)
468 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
471 dmc->curr_volt = target_volt;
478 * @dmc: device for which it is going to be set
486 static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc,
491 if (dmc->curr_volt >= target_volt)
494 ret = regulator_set_voltage(dmc->vdd_mif, target_volt,
497 dmc->curr_volt = target_volt;
504 * @dmc: device for which it is going to be set
509 static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc,
512 int idx = find_target_freq_idx(dmc, target_rate);
517 exynos5_set_bypass_dram_timings(dmc);
524 * @dmc: DMC device for which the switching is going to happen
534 exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
545 ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt);
552 ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate);
559 ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
567 * @dmc: device for which the frequency is going to be changed
588 exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
594 ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate,
603 clk_prepare_enable(dmc->fout_spll);
604 clk_prepare_enable(dmc->mout_spll);
605 clk_prepare_enable(dmc->mout_mx_mspll_ccore);
607 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore);
616 exynos5_dram_change_timings(dmc, target_rate);
618 clk_set_rate(dmc->fout_bpll, target_rate);
620 ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
624 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
632 ret = exynos5_dmc_align_target_voltage(dmc, target_volt);
635 clk_disable_unprepare(dmc->mout_mx_mspll_ccore);
636 clk_disable_unprepare(dmc->mout_spll);
637 clk_disable_unprepare(dmc->fout_spll);
645 * @dmc: device for which the frequency is going to be changed
657 static int exynos5_dmc_get_volt_freq(struct exynos5_dmc *dmc,
664 opp = devfreq_recommended_opp(dmc->dev, freq, flags);
690 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
695 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt,
701 if (target_rate == dmc->curr_rate)
704 mutex_lock(&dmc->lock);
706 ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt);
709 mutex_unlock(&dmc->lock);
713 dmc->curr_rate = target_rate;
715 mutex_unlock(&dmc->lock);
721 * @dmc: device for which the counters are going to be checked
729 static int exynos5_counters_get(struct exynos5_dmc *dmc,
740 for (i = 0; i < dmc->num_counters; i++) {
741 if (!dmc->counter[i])
744 ret = devfreq_event_get_event(dmc->counter[i], &event);
761 * @dmc: device for which the counters are going to be checked
767 static void exynos5_dmc_start_perf_events(struct exynos5_dmc *dmc,
771 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
772 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
776 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
779 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
780 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
783 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
784 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
790 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
791 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
794 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
795 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
800 * @dmc: device for which the counters are going to be checked
807 static void exynos5_dmc_perf_events_calc(struct exynos5_dmc *dmc, u64 diff_ts)
824 dmc->load = 70;
825 dmc->total = 100;
831 dmc->load = 35;
832 dmc->total = 100;
835 dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts);
840 * @dmc: device for which the counters are going to be checked
845 static void exynos5_dmc_perf_events_check(struct exynos5_dmc *dmc)
853 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
854 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
857 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
859 diff_ts = ts - dmc->last_overflow_ts[0];
860 dmc->last_overflow_ts[0] = ts;
861 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val);
863 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
864 diff_ts = ts - dmc->last_overflow_ts[1];
865 dmc->last_overflow_ts[1] = ts;
866 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val);
869 exynos5_dmc_perf_events_calc(dmc, diff_ts);
871 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
876 * @dmc: device for which the counters are going to be checked
880 static void exynos5_dmc_enable_perf_events(struct exynos5_dmc *dmc)
885 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
886 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
889 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
890 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
893 dmc->last_overflow_ts[0] = ts;
894 dmc->last_overflow_ts[1] = ts;
897 dmc->load = 99;
898 dmc->total = 100;
903 * @dmc: device for which the counters are going to be checked
907 static void exynos5_dmc_disable_perf_events(struct exynos5_dmc *dmc)
910 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
911 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
914 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
915 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
919 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
922 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
923 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
938 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
942 if (dmc->in_irq_mode) {
943 mutex_lock(&dmc->lock);
944 stat->current_frequency = dmc->curr_rate;
945 mutex_unlock(&dmc->lock);
947 stat->busy_time = dmc->load;
948 stat->total_time = dmc->total;
950 ret = exynos5_counters_get(dmc, &load, &total);
958 ret = exynos5_counters_set_event(dmc);
979 struct exynos5_dmc *dmc = dev_get_drvdata(dev);
981 mutex_lock(&dmc->lock);
982 *freq = dmc->curr_rate;
983 mutex_unlock(&dmc->lock);
1002 * @dmc: device for which the frequency is going to be set
1013 exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc,
1019 idx = find_target_freq_idx(dmc, bootloader_init_freq);
1021 aligned_freq = dmc->opp[idx].freq_hz;
1023 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz;
1030 * @dmc: device for which the frequency is going to be set
1041 static int create_timings_aligned(struct exynos5_dmc *dmc, u32 *reg_timing_row,
1055 val = dmc->timings->tRFC / clk_period_ps;
1056 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0;
1057 val = max(val, dmc->min_tck->tRFC);
1061 val = dmc->timings->tRRD / clk_period_ps;
1062 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0;
1063 val = max(val, dmc->min_tck->tRRD);
1067 val = dmc->timings->tRPab / clk_period_ps;
1068 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0;
1069 val = max(val, dmc->min_tck->tRPab);
1073 val = dmc->timings->tRCD / clk_period_ps;
1074 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0;
1075 val = max(val, dmc->min_tck->tRCD);
1079 val = dmc->timings->tRC / clk_period_ps;
1080 val += dmc->timings->tRC % clk_period_ps ? 1 : 0;
1081 val = max(val, dmc->min_tck->tRC);
1085 val = dmc->timings->tRAS / clk_period_ps;
1086 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0;
1087 val = max(val, dmc->min_tck->tRAS);
1092 val = dmc->timings->tWTR / clk_period_ps;
1093 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0;
1094 val = max(val, dmc->min_tck->tWTR);
1098 val = dmc->timings->tWR / clk_period_ps;
1099 val += dmc->timings->tWR % clk_period_ps ? 1 : 0;
1100 val = max(val, dmc->min_tck->tWR);
1104 val = dmc->timings->tRTP / clk_period_ps;
1105 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0;
1106 val = max(val, dmc->min_tck->tRTP);
1110 val = dmc->timings->tW2W_C2C / clk_period_ps;
1111 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0;
1112 val = max(val, dmc->min_tck->tW2W_C2C);
1116 val = dmc->timings->tR2R_C2C / clk_period_ps;
1117 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0;
1118 val = max(val, dmc->min_tck->tR2R_C2C);
1122 val = dmc->timings->tWL / clk_period_ps;
1123 val += dmc->timings->tWL % clk_period_ps ? 1 : 0;
1124 val = max(val, dmc->min_tck->tWL);
1128 val = dmc->timings->tDQSCK / clk_period_ps;
1129 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0;
1130 val = max(val, dmc->min_tck->tDQSCK);
1134 val = dmc->timings->tRL / clk_period_ps;
1135 val += dmc->timings->tRL % clk_period_ps ? 1 : 0;
1136 val = max(val, dmc->min_tck->tRL);
1141 val = dmc->timings->tFAW / clk_period_ps;
1142 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
1143 val = max(val, dmc->min_tck->tFAW);
1147 val = dmc->timings->tXSR / clk_period_ps;
1148 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0;
1149 val = max(val, dmc->min_tck->tXSR);
1153 val = dmc->timings->tXP / clk_period_ps;
1154 val += dmc->timings->tXP % clk_period_ps ? 1 : 0;
1155 val = max(val, dmc->min_tck->tXP);
1159 val = dmc->timings->tCKE / clk_period_ps;
1160 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0;
1161 val = max(val, dmc->min_tck->tCKE);
1165 val = dmc->timings->tMRD / clk_period_ps;
1166 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0;
1167 val = max(val, dmc->min_tck->tMRD);
1176 * @dmc: device for which the frequency is going to be set
1180 static int of_get_dram_timings(struct exynos5_dmc *dmc)
1187 np_ddr = of_parse_phandle(dmc->dev->of_node, "device-handle", 0);
1189 dev_warn(dmc->dev, "could not find 'device-handle' in DT\n");
1193 dmc->timing_row = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1195 if (!dmc->timing_row) {
1200 dmc->timing_data = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1202 if (!dmc->timing_data) {
1207 dmc->timing_power = devm_kmalloc_array(dmc->dev, TIMING_COUNT,
1209 if (!dmc->timing_power) {
1214 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dmc->dev,
1216 &dmc->timings_arr_size);
1217 if (!dmc->timings) {
1218 dev_warn(dmc->dev, "could not get timings from DT\n");
1223 dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dmc->dev);
1224 if (!dmc->min_tck) {
1225 dev_warn(dmc->dev, "could not get tck from DT\n");
1231 for (idx = 0; idx < dmc->opp_count; idx++) {
1232 freq_mhz = dmc->opp[idx].freq_hz / 1000000;
1235 ret = create_timings_aligned(dmc, &dmc->timing_row[idx],
1236 &dmc->timing_data[idx],
1237 &dmc->timing_power[idx],
1243 dmc->bypass_timing_row = dmc->timing_row[idx - 1];
1244 dmc->bypass_timing_data = dmc->timing_data[idx - 1];
1245 dmc->bypass_timing_power = dmc->timing_power[idx - 1];
1254 * @dmc: DMC structure containing needed fields
1259 static int exynos5_dmc_init_clks(struct exynos5_dmc *dmc)
1266 dmc->fout_spll = devm_clk_get(dmc->dev, "fout_spll");
1267 if (IS_ERR(dmc->fout_spll))
1268 return PTR_ERR(dmc->fout_spll);
1270 dmc->fout_bpll = devm_clk_get(dmc->dev, "fout_bpll");
1271 if (IS_ERR(dmc->fout_bpll))
1272 return PTR_ERR(dmc->fout_bpll);
1274 dmc->mout_mclk_cdrex = devm_clk_get(dmc->dev, "mout_mclk_cdrex");
1275 if (IS_ERR(dmc->mout_mclk_cdrex))
1276 return PTR_ERR(dmc->mout_mclk_cdrex);
1278 dmc->mout_bpll = devm_clk_get(dmc->dev, "mout_bpll");
1279 if (IS_ERR(dmc->mout_bpll))
1280 return PTR_ERR(dmc->mout_bpll);
1282 dmc->mout_mx_mspll_ccore = devm_clk_get(dmc->dev,
1284 if (IS_ERR(dmc->mout_mx_mspll_ccore))
1285 return PTR_ERR(dmc->mout_mx_mspll_ccore);
1287 dmc->mout_spll = devm_clk_get(dmc->dev, "ff_dout_spll2");
1288 if (IS_ERR(dmc->mout_spll)) {
1289 dmc->mout_spll = devm_clk_get(dmc->dev, "mout_sclk_spll");
1290 if (IS_ERR(dmc->mout_spll))
1291 return PTR_ERR(dmc->mout_spll);
1297 dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex);
1298 dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate);
1299 exynos5_dmc_df_profile.initial_freq = dmc->curr_rate;
1301 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate,
1306 dmc->curr_volt = target_volt;
1308 ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll);
1312 clk_prepare_enable(dmc->fout_bpll);
1313 clk_prepare_enable(dmc->mout_bpll);
1319 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp);
1321 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp);
1328 * @dmc: DMC for which it does the setup
1335 static int exynos5_performance_counters_init(struct exynos5_dmc *dmc)
1339 dmc->num_counters = devfreq_event_get_edev_count(dmc->dev,
1341 if (dmc->num_counters < 0) {
1342 dev_err(dmc->dev, "could not get devfreq-event counters\n");
1343 return dmc->num_counters;
1346 dmc->counter = devm_kcalloc(dmc->dev, dmc->num_counters,
1347 sizeof(*dmc->counter), GFP_KERNEL);
1348 if (!dmc->counter)
1351 for (i = 0; i < dmc->num_counters; i++) {
1352 dmc->counter[i] =
1353 devfreq_event_get_edev_by_phandle(dmc->dev,
1355 if (IS_ERR_OR_NULL(dmc->counter[i]))
1359 ret = exynos5_counters_enable_edev(dmc);
1361 dev_err(dmc->dev, "could not enable event counter\n");
1365 ret = exynos5_counters_set_event(dmc);
1367 exynos5_counters_disable_edev(dmc);
1368 dev_err(dmc->dev, "could not set event counter\n");
1377 * @dmc: device which is used for changing this feature
1384 static inline int exynos5_dmc_set_pause_on_switching(struct exynos5_dmc *dmc)
1389 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val);
1394 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val);
1402 struct exynos5_dmc *dmc = priv;
1404 mutex_lock(&dmc->df->lock);
1405 exynos5_dmc_perf_events_check(dmc);
1406 res = update_devfreq(dmc->df);
1407 mutex_unlock(&dmc->df->lock);
1410 dev_warn(dmc->dev, "devfreq failed with %d\n", res);
1430 struct exynos5_dmc *dmc;
1433 dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL);
1434 if (!dmc)
1437 mutex_init(&dmc->lock);
1439 dmc->dev = dev;
1440 platform_set_drvdata(pdev, dmc);
1442 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
1443 if (IS_ERR(dmc->base_drexi0))
1444 return PTR_ERR(dmc->base_drexi0);
1446 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
1447 if (IS_ERR(dmc->base_drexi1))
1448 return PTR_ERR(dmc->base_drexi1);
1450 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np,
1452 if (IS_ERR(dmc->clk_regmap))
1453 return PTR_ERR(dmc->clk_regmap);
1455 ret = exynos5_init_freq_table(dmc, &exynos5_dmc_df_profile);
1461 dmc->vdd_mif = devm_regulator_get(dev, "vdd");
1462 if (IS_ERR(dmc->vdd_mif)) {
1463 ret = PTR_ERR(dmc->vdd_mif);
1467 ret = exynos5_dmc_init_clks(dmc);
1471 ret = of_get_dram_timings(dmc);
1477 ret = exynos5_dmc_set_pause_on_switching(dmc);
1489 dev_name(dev), dmc);
1497 dev_name(dev), dmc);
1507 dmc->gov_data.upthreshold = 55;
1508 dmc->gov_data.downdifferential = 5;
1510 exynos5_dmc_enable_perf_events(dmc);
1512 dmc->in_irq_mode = 1;
1514 ret = exynos5_performance_counters_init(dmc);
1524 dmc->gov_data.upthreshold = 10;
1525 dmc->gov_data.downdifferential = 5;
1530 dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile,
1532 &dmc->gov_data);
1534 if (IS_ERR(dmc->df)) {
1535 ret = PTR_ERR(dmc->df);
1539 if (dmc->in_irq_mode)
1540 exynos5_dmc_start_perf_events(dmc, PERF_COUNTER_START_VALUE);
1542 dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode);
1547 if (dmc->in_irq_mode)
1548 exynos5_dmc_disable_perf_events(dmc);
1550 exynos5_counters_disable_edev(dmc);
1552 clk_disable_unprepare(dmc->mout_bpll);
1553 clk_disable_unprepare(dmc->fout_bpll);
1568 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev);
1570 if (dmc->in_irq_mode)
1571 exynos5_dmc_disable_perf_events(dmc);
1573 exynos5_counters_disable_edev(dmc);
1575 clk_disable_unprepare(dmc->mout_bpll);
1576 clk_disable_unprepare(dmc->fout_bpll);
1578 dev_pm_opp_remove_table(dmc->dev);
1584 { .compatible = "samsung,exynos5422-dmc", },
1593 .name = "exynos5-dmc",