Lines Matching defs:base_drexi1
117 * @base_drexi1: DREX1 registers mapping
157 void __iomem *base_drexi1;
397 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1);
401 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1);
405 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1);
437 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0);
441 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0);
445 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0);
772 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC);
776 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC);
780 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
784 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC);
791 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC);
795 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC);
854 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
863 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC);
886 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON);
890 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG);
911 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC);
915 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC);
919 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC);
923 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC);
1446 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1);
1447 if (IS_ERR(dmc->base_drexi1))
1448 return PTR_ERR(dmc->base_drexi1);