Lines Matching defs:base_drexi0
116 * @base_drexi0: DREX0 registers mapping
156 void __iomem *base_drexi0;
392 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
395 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1);
399 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1);
403 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1);
432 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF);
435 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0);
439 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0);
443 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0);
771 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC);
775 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC);
779 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
783 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC);
790 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC);
794 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC);
853 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
857 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC);
885 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON);
889 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG);
910 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC);
914 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC);
918 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC);
922 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC);
1442 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0);
1443 if (IS_ERR(dmc->base_drexi0))
1444 return PTR_ERR(dmc->base_drexi0);