Lines Matching refs:val
373 u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
383 val = t_refi * freq_khz / 10000;
384 ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
393 u32 tim1 = 0, val = 0;
395 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
396 tim1 |= val << T_WTR_SHIFT;
399 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
401 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
402 tim1 |= (val - 1) << T_RRD_SHIFT;
404 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
405 tim1 |= val << T_RC_SHIFT;
407 val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
408 tim1 |= (val - 1) << T_RAS_SHIFT;
410 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
411 tim1 |= val << T_WR_SHIFT;
413 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
414 tim1 |= val << T_RCD_SHIFT;
416 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
417 tim1 |= val << T_RP_SHIFT;
426 u32 tim1 = 0, val = 0;
428 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
429 tim1 = val << T_WTR_SHIFT;
436 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
438 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
439 val = max(min_tck->tRRD, val) - 1;
441 tim1 |= val << T_RRD_SHIFT;
443 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
444 tim1 |= (val - 1) << T_RC_SHIFT;
446 val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
447 val = max(min_tck->tRASmin, val) - 1;
448 tim1 |= val << T_RAS_SHIFT;
450 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
451 tim1 |= val << T_WR_SHIFT;
453 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
454 tim1 |= (val - 1) << T_RCD_SHIFT;
456 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
457 tim1 |= (val - 1) << T_RP_SHIFT;
467 u32 tim2 = 0, val = 0;
469 val = min_tck->tCKE - 1;
470 tim2 |= val << T_CKE_SHIFT;
472 val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
473 tim2 |= val << T_RTP_SHIFT;
476 val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
477 tim2 |= val << T_XSNR_SHIFT;
480 tim2 |= val << T_XSRD_SHIFT;
482 val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
483 tim2 |= val << T_XP_SHIFT;
493 u32 tim3 = 0, val = 0, t_dqsck;
495 val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
496 val = val > 0xF ? 0xF : val;
497 tim3 |= val << T_RAS_MAX_SHIFT;
499 val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
500 tim3 |= val << T_RFC_SHIFT;
505 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
507 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
509 tim3 |= val << T_TDQSCKMAX_SHIFT;
511 val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
512 tim3 |= val << ZQ_ZQCS_SHIFT;
514 val = DIV_ROUND_UP(timings->tCKESR, t_ck);
515 val = max(min_tck->tCKESR, val) - 1;
516 tim3 |= val << T_CKESR_SHIFT;
521 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
522 tim3 |= val << T_PDLL_UL_SHIFT;
531 u32 zq = 0, val = 0;
533 val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
534 zq |= val << ZQ_REFINTERVAL_SHIFT;
536 val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
537 zq |= val << ZQ_ZQCL_MULT_SHIFT;
539 val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
540 zq |= val << ZQ_ZQINIT_MULT_SHIFT;
551 val = cs1_used ? 1 : 0;
552 zq |= val << ZQ_CS1EN_SHIFT;
594 u32 idle = 0, val = 0;
601 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
603 val = 0x1FF;
609 idle |= val << DLL_CALIB_INTERVAL_SHIFT;
617 u32 calib = 0, val = 0;
620 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
622 val = 0; /* Disabled when voltage is stable */
624 calib |= val << DLL_CALIB_INTERVAL_SHIFT;
633 u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
635 val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
636 phy |= val << READ_LATENCY_SHIFT_4D;
639 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
641 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
643 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
645 phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;