Lines Matching refs:tim3
493 u32 tim3 = 0, val = 0, t_dqsck;
497 tim3 |= val << T_RAS_MAX_SHIFT;
500 tim3 |= val << T_RFC_SHIFT;
509 tim3 |= val << T_TDQSCKMAX_SHIFT;
512 tim3 |= val << ZQ_ZQCS_SHIFT;
516 tim3 |= val << T_CKESR_SHIFT;
519 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
522 tim3 |= val << T_PDLL_UL_SHIFT;
525 return tim3;
880 u32 tim1, tim3, ref_ctrl, type;
887 tim3 = regs->sdram_tim3_shdw;
899 tim3 = regs->sdram_tim3_shdw_derated;
905 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);