Lines Matching defs:tim1
393 u32 tim1 = 0, val = 0;
396 tim1 |= val << T_WTR_SHIFT;
402 tim1 |= (val - 1) << T_RRD_SHIFT;
405 tim1 |= val << T_RC_SHIFT;
408 tim1 |= (val - 1) << T_RAS_SHIFT;
411 tim1 |= val << T_WR_SHIFT;
414 tim1 |= val << T_RCD_SHIFT;
417 tim1 |= val << T_RP_SHIFT;
419 return tim1;
426 u32 tim1 = 0, val = 0;
429 tim1 = val << T_WTR_SHIFT;
441 tim1 |= val << T_RRD_SHIFT;
444 tim1 |= (val - 1) << T_RC_SHIFT;
448 tim1 |= val << T_RAS_SHIFT;
451 tim1 |= val << T_WR_SHIFT;
454 tim1 |= (val - 1) << T_RCD_SHIFT;
457 tim1 |= (val - 1) << T_RP_SHIFT;
459 return tim1;
880 u32 tim1, tim3, ref_ctrl, type;
886 tim1 = regs->sdram_tim1_shdw;
898 tim1 = regs->sdram_tim1_shdw_derated;
904 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);