Lines Matching defs:base
42 * @base: base address of memory-mapped IO registers.
62 void __iomem *base;
190 void __iomem *base = emif->base;
192 width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
205 void __iomem *base = emif->base;
207 cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
215 void __iomem *base = emif->base;
251 temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
254 writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
797 void __iomem *base;
799 base = emif->base;
802 writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
803 temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
808 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
809 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
830 void __iomem *base = emif->base;
832 writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
833 writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
835 base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
840 writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
841 writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
842 writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
853 void __iomem *base = emif->base;
866 writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
881 void __iomem *base = emif->base;
904 writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
905 writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
906 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
909 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
971 void __iomem *base = emif->base;
976 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
977 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
985 ret = handle_temp_alert(base, emif);
992 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
993 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1036 void __iomem *base = emif->base;
1038 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1039 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1041 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1042 base + EMIF_LL_OCP_INTERRUPT_STATUS);
1047 void __iomem *base = emif->base;
1050 writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1051 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1053 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1054 base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1063 void __iomem *base = emif->base;
1073 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1079 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1094 void __iomem *base = emif->base;
1109 writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1114 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1125 writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1133 writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1134 writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1135 writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1136 writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1137 writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1138 writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1139 writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1140 writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1141 writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1142 writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1143 writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1144 writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1145 writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1146 writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1147 writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1148 writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1149 writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1150 writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1151 writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1152 writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1153 writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1518 emif->base = devm_ioremap_resource(emif->dev, res);
1519 if (IS_ERR(emif->base))
1546 __func__, emif->base, irq);