Lines Matching refs:temp
355 u32 temp;
358 temp = 0x82 | MCI_REGISTER_DATA_BYTE0 | ((value & 0x000000FF) << 8);
359 temp = temp << 10;
360 status = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
363 temp = temp | (0x05 << 10);
364 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
367 temp = 0x82 | MCI_REGISTER_DATA_BYTE1 | (value & 0x0000FF00);
368 temp = temp << 10;
369 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
370 temp = temp | (0x05 << 10);
371 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
374 temp = 0x82 | MCI_REGISTER_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
375 temp = temp << 10;
376 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
377 temp = temp | (0x05 << 10);
378 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
381 temp = 0x82 | MCI_REGISTER_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
382 temp = temp << 10;
383 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
384 temp = temp | (0x05 << 10);
385 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
388 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x000000FF) << 8);
389 temp = temp << 10;
390 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
391 temp = temp | (0x05 << 10);
392 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
395 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0x0000FF00);
396 temp = temp << 10;
397 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
398 temp = temp | (0x05 << 10);
399 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
402 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
403 temp = temp << 10;
404 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
405 temp = temp | (0x05 << 10);
406 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
414 u32 temp;
418 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
419 temp = temp << 10;
420 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
421 temp = temp | ((0x05) << 10);
422 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
425 temp = 0x82 | MCI_REGISTER_ADDRESS_BYTE1 | (address & 0xFF00);
426 temp = temp << 10;
427 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
428 temp = temp | ((0x05) << 10);
429 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
432 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
433 temp = temp << 10;
434 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
435 temp = temp | ((0x05) << 10);
436 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
445 temp = (0x82 | MCI_REGISTER_DATA_BYTE0) << 10;
446 set_itvc_reg(dev, ITVC_READ_DIR, temp);
447 temp = ((0x81 | MCI_REGISTER_DATA_BYTE0) << 10);
448 set_itvc_reg(dev, ITVC_READ_DIR, temp);
449 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
450 return_value |= ((temp & 0x03FC0000) >> 18);
454 temp = (0x82 | MCI_REGISTER_DATA_BYTE1) << 10;
455 set_itvc_reg(dev, ITVC_READ_DIR, temp);
456 temp = ((0x81 | MCI_REGISTER_DATA_BYTE1) << 10);
457 set_itvc_reg(dev, ITVC_READ_DIR, temp);
458 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
460 return_value |= ((temp & 0x03FC0000) >> 10);
464 temp = (0x82 | MCI_REGISTER_DATA_BYTE2) << 10;
465 set_itvc_reg(dev, ITVC_READ_DIR, temp);
466 temp = ((0x81 | MCI_REGISTER_DATA_BYTE2) << 10);
467 set_itvc_reg(dev, ITVC_READ_DIR, temp);
468 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
469 return_value |= ((temp & 0x03FC0000) >> 2);
473 temp = (0x82 | MCI_REGISTER_DATA_BYTE3) << 10;
474 set_itvc_reg(dev, ITVC_READ_DIR, temp);
475 temp = ((0x81 | MCI_REGISTER_DATA_BYTE3) << 10);
476 set_itvc_reg(dev, ITVC_READ_DIR, temp);
477 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
478 return_value |= ((temp & 0x03FC0000) << 6);
489 u32 temp;
492 temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
493 temp = temp << 10;
494 ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
497 temp = temp | (0x05 << 10);
498 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
501 temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
502 temp = temp << 10;
503 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
504 temp = temp | (0x05 << 10);
505 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
508 temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
509 temp = temp << 10;
510 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
511 temp = temp | (0x05 << 10);
512 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
515 temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
516 temp = temp << 10;
517 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
518 temp = temp | (0x05 << 10);
519 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
522 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
524 temp = temp << 10;
525 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
526 temp = temp | (0x05 << 10);
527 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
530 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
531 temp = temp << 10;
532 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
533 temp = temp | (0x05 << 10);
534 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
537 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
538 temp = temp << 10;
539 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
540 temp = temp | (0x05 << 10);
541 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
551 u32 temp = 0;
556 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
558 temp = temp << 10;
559 ret = set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
562 temp = temp | (0x05 << 10);
563 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
566 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
567 temp = temp << 10;
568 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
569 temp = temp | (0x05 << 10);
570 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
573 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
574 temp = temp << 10;
575 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
576 temp = temp | (0x05 << 10);
577 set_itvc_reg(dev, ITVC_WRITE_DIR, temp);
584 temp = (0x82 | MCI_MEMORY_DATA_BYTE3) << 10;
585 set_itvc_reg(dev, ITVC_READ_DIR, temp);
586 temp = ((0x81 | MCI_MEMORY_DATA_BYTE3) << 10);
587 set_itvc_reg(dev, ITVC_READ_DIR, temp);
588 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
589 return_value |= ((temp & 0x03FC0000) << 6);
593 temp = (0x82 | MCI_MEMORY_DATA_BYTE2) << 10;
594 set_itvc_reg(dev, ITVC_READ_DIR, temp);
595 temp = ((0x81 | MCI_MEMORY_DATA_BYTE2) << 10);
596 set_itvc_reg(dev, ITVC_READ_DIR, temp);
597 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
598 return_value |= ((temp & 0x03FC0000) >> 2);
602 temp = (0x82 | MCI_MEMORY_DATA_BYTE1) << 10;
603 set_itvc_reg(dev, ITVC_READ_DIR, temp);
604 temp = ((0x81 | MCI_MEMORY_DATA_BYTE1) << 10);
605 set_itvc_reg(dev, ITVC_READ_DIR, temp);
606 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
607 return_value |= ((temp & 0x03FC0000) >> 10);
611 temp = (0x82 | MCI_MEMORY_DATA_BYTE0) << 10;
612 set_itvc_reg(dev, ITVC_READ_DIR, temp);
613 temp = ((0x81 | MCI_MEMORY_DATA_BYTE0) << 10);
614 set_itvc_reg(dev, ITVC_READ_DIR, temp);
615 get_itvc_reg(dev, ITVC_READ_DIR, &temp);
616 return_value |= ((temp & 0x03FC0000) >> 18);
849 u32 temp = 0;
852 temp = 0x82 | MCI_MEMORY_DATA_BYTE0 | ((value & 0x000000FF) << 8);
853 temp = temp << 10;
854 *p_fw_image = temp;
856 temp = temp | (0x05 << 10);
857 *p_fw_image = temp;
861 temp = 0x82 | MCI_MEMORY_DATA_BYTE1 | (value & 0x0000FF00);
862 temp = temp << 10;
863 *p_fw_image = temp;
865 temp = temp | (0x05 << 10);
866 *p_fw_image = temp;
870 temp = 0x82 | MCI_MEMORY_DATA_BYTE2 | ((value & 0x00FF0000) >> 8);
871 temp = temp << 10;
872 *p_fw_image = temp;
874 temp = temp | (0x05 << 10);
875 *p_fw_image = temp;
879 temp = 0x82 | MCI_MEMORY_DATA_BYTE3 | ((value & 0xFF000000) >> 16);
880 temp = temp << 10;
881 *p_fw_image = temp;
883 temp = temp | (0x05 << 10);
884 *p_fw_image = temp;
888 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
890 temp = temp << 10;
891 *p_fw_image = temp;
893 temp = temp | (0x05 << 10);
894 *p_fw_image = temp;
898 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
899 temp = temp << 10;
900 *p_fw_image = temp;
902 temp = temp | (0x05 << 10);
903 *p_fw_image = temp;
907 temp = 0x82 | MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF) << 8);
908 temp = temp << 10;
909 *p_fw_image = temp;
911 temp = temp | (0x05 << 10);
912 *p_fw_image = temp;