Lines Matching defs:state
64 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val)
69 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf));
75 static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val)
79 .addr = state->i2c->addr,
85 .addr = state->i2c->addr,
93 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs));
100 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast)
103 state->regs[0x03] |= 0x01; /* set fast search mode */
105 state->regs[0x03] &= ~0x01 & 0xff;
107 return reg_write(state, 0x03, state->regs[0x03]);
110 static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state)
114 state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */
115 state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */
116 state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */
117 ret = reg_write(state, 0x01, state->regs[0x01]);
119 ret = reg_write(state, 0x05, state->regs[0x05]);
122 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
123 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
131 struct qm1d1c0042_state *state;
134 state = fe->tuner_priv;
138 state->cfg.fe = cfg->fe;
141 dev_warn(&state->i2c->dev,
143 state->cfg.xtal_freq = default_cfg.xtal_freq;
145 state->cfg.lpf = cfg->lpf;
146 state->cfg.fast_srch = cfg->fast_srch;
149 state->cfg.lpf_wait = cfg->lpf_wait;
151 state->cfg.lpf_wait = default_cfg.lpf_wait;
154 state->cfg.fast_srch_wait = cfg->fast_srch_wait;
156 state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
159 state->cfg.normal_srch_wait = cfg->normal_srch_wait;
161 state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
181 struct qm1d1c0042_state *state;
188 state = fe->tuner_priv;
191 state->regs[0x08] &= 0xf0;
192 state->regs[0x08] |= 0x09;
194 state->regs[0x13] &= 0x9f;
195 state->regs[0x13] |= 0x20;
198 val = state->regs[0x02] & 0x0f;
205 ret = reg_write(state, 0x02, val);
209 a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq);
211 state->regs[0x06] &= 0x40;
212 state->regs[0x06] |= (a - 12) / 4;
213 ret = reg_write(state, 0x06, state->regs[0x06]);
217 state->regs[0x07] &= 0xf0;
218 state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f;
219 ret = reg_write(state, 0x07, state->regs[0x07]);
224 val = state->regs[0x08];
225 if (state->cfg.lpf) {
230 ret = reg_write(state, 0x08, val);
235 * b = (freq / state->cfg.xtal_freq - a) << 20;
239 b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
247 state->regs[0x09] &= 0xc0;
248 state->regs[0x09] |= (sd >> 16) & 0x3f;
249 state->regs[0x0a] = (sd >> 8) & 0xff;
250 state->regs[0x0b] = sd & 0xff;
251 ret = reg_write(state, 0x09, state->regs[0x09]);
253 ret = reg_write(state, 0x0a, state->regs[0x0a]);
255 ret = reg_write(state, 0x0b, state->regs[0x0b]);
259 if (!state->cfg.lpf) {
261 ret = reg_write(state, 0x13, state->regs[0x13]);
267 mask = state->cfg.lpf ? 0x3f : 0x7f;
268 val = state->regs[0x0c] & mask;
269 ret = reg_write(state, 0x0c, val);
273 val = state->regs[0x0c] | ~mask;
274 ret = reg_write(state, 0x0c, val);
278 if (state->cfg.lpf)
279 msleep(state->cfg.lpf_wait);
280 else if (state->regs[0x03] & 0x01)
281 msleep(state->cfg.fast_srch_wait);
283 msleep(state->cfg.normal_srch_wait);
285 if (state->cfg.lpf) {
287 ret = reg_write(state, 0x08, 0x09);
292 ret = reg_write(state, 0x13, state->regs[0x13]);
301 struct qm1d1c0042_state *state;
304 state = fe->tuner_priv;
305 state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */
306 state->regs[0x01] |= 1 << 0; /* STDBY */
307 state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */
308 ret = reg_write(state, 0x05, state->regs[0x05]);
310 ret = reg_write(state, 0x01, state->regs[0x01]);
312 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
319 struct qm1d1c0042_state *state;
323 state = fe->tuner_priv;
325 reg_write(state, 0x01, 0x0c);
326 reg_write(state, 0x01, 0x0c);
328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
333 ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
338 ret = reg_read(state, 0x00, &val);
350 memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
353 state->regs[0x0c] |= 0x40;
354 ret = reg_write(state, 0x0c, state->regs[0x0c]);
357 msleep(state->cfg.lpf_wait);
361 ret = reg_write(state, i, state->regs[i]);
366 ret = reg_write(state, i, state->regs[i]);
371 ret = qm1d1c0042_wakeup(state);
375 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
382 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n",
407 struct qm1d1c0042_state *state;
411 state = kzalloc(sizeof(*state), GFP_KERNEL);
412 if (!state)
414 state->i2c = client;
418 fe->tuner_priv = state;
422 i2c_set_clientdata(client, &state->cfg);
429 struct qm1d1c0042_state *state;
431 state = cfg_to_state(i2c_get_clientdata(client));
432 state->cfg.fe->tuner_priv = NULL;
433 kfree(state);