Lines Matching defs:cfg
54 struct qm1d1c0042_config cfg;
61 return container_of(c, struct qm1d1c0042_state, cfg);
123 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id);
132 struct qm1d1c0042_config *cfg;
135 cfg = priv_cfg;
137 if (cfg->fe)
138 state->cfg.fe = cfg->fe;
140 if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT)
143 state->cfg.xtal_freq = default_cfg.xtal_freq;
145 state->cfg.lpf = cfg->lpf;
146 state->cfg.fast_srch = cfg->fast_srch;
148 if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT)
149 state->cfg.lpf_wait = cfg->lpf_wait;
151 state->cfg.lpf_wait = default_cfg.lpf_wait;
153 if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
154 state->cfg.fast_srch_wait = cfg->fast_srch_wait;
156 state->cfg.fast_srch_wait = default_cfg.fast_srch_wait;
158 if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT)
159 state->cfg.normal_srch_wait = cfg->normal_srch_wait;
161 state->cfg.normal_srch_wait = default_cfg.normal_srch_wait;
209 a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq);
225 if (state->cfg.lpf) {
235 * b = (freq / state->cfg.xtal_freq - a) << 20;
239 b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq)
259 if (!state->cfg.lpf) {
267 mask = state->cfg.lpf ? 0x3f : 0x7f;
278 if (state->cfg.lpf)
279 msleep(state->cfg.lpf_wait);
281 msleep(state->cfg.fast_srch_wait);
283 msleep(state->cfg.normal_srch_wait);
285 if (state->cfg.lpf) {
357 msleep(state->cfg.lpf_wait);
375 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch);
408 struct qm1d1c0042_config *cfg;
416 cfg = client->dev.platform_data;
417 fe = cfg->fe;
419 qm1d1c0042_set_config(fe, cfg);
422 i2c_set_clientdata(client, &state->cfg);
432 state->cfg.fe->tuner_priv = NULL;