Lines Matching refs:FminBin
2313 u32 Fmax, Fmin, FmaxBin, FminBin;
2474 FminBin = 28000000UL ;
2485 Fmin = FminBin ;
2487 FminBin = 42500000UL ;
2489 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2498 Fmin = FminBin ;
2500 FminBin = 56000000UL ;
2502 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2511 Fmin = FminBin ;
2513 FminBin = 85000000UL ;
2515 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2524 Fmin = FminBin ;
2526 FminBin = 112000000UL ;
2528 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2537 Fmin = FminBin ;
2539 FminBin = 170000000UL ;
2541 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2550 Fmin = FminBin ;
2552 FminBin = 225000000UL ;
2554 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2563 Fmin = FminBin ;
2565 FminBin = 300000000UL ;
2567 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2578 FminBin = 340000000UL ;
2580 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2589 Fmin = FminBin ;
2591 FminBin = 450000000UL ;
2593 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2602 Fmin = FminBin ;
2604 FminBin = 680000000UL ;
2606 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2615 Fmin = FminBin ;
2662 FminBin = 33000000UL ;
2664 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2669 Fmin = FminBin ;
2671 FminBin = 50000000UL ;
2673 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2678 Fmin = FminBin ;
2680 FminBin = 67000000UL ;
2682 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2687 Fmin = FminBin ;
2689 FminBin = 100000000UL ;
2691 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2696 Fmin = FminBin ;
2698 FminBin = 150000000UL ;
2700 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2705 Fmin = FminBin ;
2707 FminBin = 200000000UL ;
2709 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2714 Fmin = FminBin ;
2716 FminBin = 300000000UL ;
2718 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2723 Fmin = FminBin ;
2725 FminBin = 400000000UL ;
2727 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2732 Fmin = FminBin ;
2734 FminBin = 600000000UL ;
2736 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {