Lines Matching refs:state
239 static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len)
241 struct dvb_frontend *fe = state->frontend;
245 .addr = state->config->tuner_address,
258 ret = i2c_transfer(state->i2c, &msg, 1);
271 static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
280 status = mt2063_write(state, reg, &val, 1);
284 state->reg[reg] = val;
292 static int mt2063_read(struct mt2063_state *state,
296 struct dvb_frontend *fe = state->frontend;
308 .addr = state->config->tuner_address,
313 .addr = state->config->tuner_address,
320 status = i2c_transfer(state->i2c, msg, 2);
904 * @state: struct mt2063_state pointer
908 static int mt2063_lockStatus(struct mt2063_state *state)
921 if (state->tuner_id == MT2063_B0)
925 status = mt2063_read(state, MT2063_REG_LO_STATUS,
926 &state->reg[MT2063_REG_LO_STATUS], 1);
931 if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) ==
1017 static u32 mt2063_get_dnc_output_enable(struct mt2063_state *state,
1022 if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */
1023 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1028 if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */
1039 static u32 mt2063_set_dnc_output_enable(struct mt2063_state *state,
1050 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1051 if (state->reg[MT2063_REG_DNC_GAIN] !=
1054 mt2063_setreg(state,
1058 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1059 if (state->reg[MT2063_REG_VGA_GAIN] !=
1062 mt2063_setreg(state,
1066 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1067 if (state->reg[MT2063_REG_RSVD_20] !=
1070 mt2063_setreg(state,
1076 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1077 if (state->reg[MT2063_REG_DNC_GAIN] !=
1080 mt2063_setreg(state,
1084 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1085 if (state->reg[MT2063_REG_VGA_GAIN] !=
1088 mt2063_setreg(state,
1092 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1093 if (state->reg[MT2063_REG_RSVD_20] !=
1096 mt2063_setreg(state,
1102 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1103 if (state->reg[MT2063_REG_DNC_GAIN] !=
1106 mt2063_setreg(state,
1110 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1111 if (state->reg[MT2063_REG_VGA_GAIN] !=
1114 mt2063_setreg(state,
1118 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1119 if (state->reg[MT2063_REG_RSVD_20] !=
1122 mt2063_setreg(state,
1128 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1129 if (state->reg[MT2063_REG_DNC_GAIN] !=
1132 mt2063_setreg(state,
1136 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1137 if (state->reg[MT2063_REG_VGA_GAIN] !=
1140 mt2063_setreg(state,
1144 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1145 if (state->reg[MT2063_REG_RSVD_20] !=
1148 mt2063_setreg(state,
1167 * @state: ptr to mt2063_state structure
1173 static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1188 (state->
1192 if (state->reg[MT2063_REG_PD1_TGT] != val)
1193 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1198 u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) |
1200 if (state->reg[MT2063_REG_CTRL_2C] != val)
1201 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
1207 (state->
1210 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
1212 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
1215 (state->reg[MT2063_REG_FIFF_CTRL] | 0x01);
1217 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1219 (state->
1222 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1227 status |= mt2063_get_dnc_output_enable(state, &longval);
1228 status |= mt2063_set_dnc_output_enable(state, longval);
1232 u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) |
1234 if (state->reg[MT2063_REG_LNA_OV] != val)
1235 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
1240 u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) |
1242 if (state->reg[MT2063_REG_LNA_TGT] != val)
1243 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1248 u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) |
1250 if (state->reg[MT2063_REG_RF_OV] != val)
1251 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
1256 u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) |
1258 if (state->reg[MT2063_REG_PD1_TGT] != val)
1259 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1265 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
1267 val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) |
1269 if (state->reg[MT2063_REG_FIF_OV] != val)
1270 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
1275 u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) |
1277 if (state->reg[MT2063_REG_PD2_TGT] != val)
1278 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
1283 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) |
1285 if (state->reg[MT2063_REG_LNA_TGT] != val)
1286 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1291 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) |
1293 if (state->reg[MT2063_REG_PD1_TGT] != val)
1294 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1298 state->rcvr_mode = Mode;
1300 mt2063_mode_name[state->rcvr_mode]);
1315 static u32 MT2063_ClearPowerMaskBits(struct mt2063_state *state,
1323 state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8);
1325 mt2063_write(state,
1327 &state->reg[MT2063_REG_PWR_2], 1);
1330 state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF);
1332 mt2063_write(state,
1334 &state->reg[MT2063_REG_PWR_1], 1);
1345 static u32 MT2063_SoftwareShutdown(struct mt2063_state *state, u8 Shutdown)
1351 state->reg[MT2063_REG_PWR_1] |= 0x04;
1353 state->reg[MT2063_REG_PWR_1] &= ~0x04;
1355 status = mt2063_write(state,
1357 &state->reg[MT2063_REG_PWR_1], 1);
1360 state->reg[MT2063_REG_BYP_CTRL] =
1361 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40;
1363 mt2063_write(state,
1365 &state->reg[MT2063_REG_BYP_CTRL],
1367 state->reg[MT2063_REG_BYP_CTRL] =
1368 (state->reg[MT2063_REG_BYP_CTRL] & 0x9F);
1370 mt2063_write(state,
1372 &state->reg[MT2063_REG_BYP_CTRL],
1482 * @state: ptr to tuner data structure
1487 static u32 FindClearTuneFilter(struct mt2063_state *state, u32 f_in)
1497 if (state->CTFiltMax[idx] >= f_in) {
1508 static u32 MT2063_Tune(struct mt2063_state *state, u32 f_in)
1530 if ((state->AS_Data.f_out < MT2063_MIN_FOUT_FREQ)
1531 || (state->AS_Data.f_out > MT2063_MAX_FOUT_FREQ))
1537 ofLO1 = state->AS_Data.f_LO1;
1538 ofLO2 = state->AS_Data.f_LO2;
1543 if (state->ctfilt_sw == 1) {
1544 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
1545 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
1547 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
1549 val = state->reg[MT2063_REG_CTUNE_OV];
1550 RFBand = FindClearTuneFilter(state, f_in);
1551 state->reg[MT2063_REG_CTUNE_OV] =
1552 (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F)
1554 if (state->reg[MT2063_REG_CTUNE_OV] != val) {
1556 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
1565 mt2063_read(state,
1567 &state->reg[MT2063_REG_FIFFC], 1);
1568 fiffc = state->reg[MT2063_REG_FIFFC];
1573 state->AS_Data.f_in = f_in;
1575 state->AS_Data.f_if1_Request =
1576 MT2063_Round_fLO(state->AS_Data.f_if1_Request + f_in,
1577 state->AS_Data.f_LO1_Step,
1578 state->AS_Data.f_ref) - f_in;
1584 MT2063_ResetExclZones(&state->AS_Data);
1586 f_IF1 = MT2063_ChooseFirstIF(&state->AS_Data);
1588 state->AS_Data.f_LO1 =
1589 MT2063_Round_fLO(f_IF1 + f_in, state->AS_Data.f_LO1_Step,
1590 state->AS_Data.f_ref);
1592 state->AS_Data.f_LO2 =
1593 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
1594 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1600 status |= MT2063_AvoidSpurs(&state->AS_Data);
1606 state->AS_Data.f_LO1 =
1607 MT2063_CalcLO1Mult(&LO1, &Num1, state->AS_Data.f_LO1,
1608 state->AS_Data.f_LO1_Step, state->AS_Data.f_ref);
1609 state->AS_Data.f_LO2 =
1610 MT2063_Round_fLO(state->AS_Data.f_LO1 - state->AS_Data.f_out - f_in,
1611 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1612 state->AS_Data.f_LO2 =
1613 MT2063_CalcLO2Mult(&LO2, &Num2, state->AS_Data.f_LO2,
1614 state->AS_Data.f_LO2_Step, state->AS_Data.f_ref);
1619 if ((state->AS_Data.f_LO1 < MT2063_MIN_UPC_FREQ)
1620 || (state->AS_Data.f_LO1 > MT2063_MAX_UPC_FREQ))
1622 if ((state->AS_Data.f_LO2 < MT2063_MIN_DNC_FREQ)
1623 || (state->AS_Data.f_LO2 > MT2063_MAX_DNC_FREQ))
1626 if (state->tuner_id == MT2063_B0)
1633 if ((ofLO1 != state->AS_Data.f_LO1)
1634 || (ofLO2 != state->AS_Data.f_LO2)
1635 || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) !=
1645 (state->AS_Data.f_LO1 -
1646 f_in) / (state->AS_Data.f_ref / 64) - 8 * (u32) fiffc -
1656 state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */
1657 state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */
1658 state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */
1660 state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */
1661 state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */
1668 status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */
1669 if (state->tuner_id == MT2063_B0) {
1671 status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */
1674 if (state->reg[MT2063_REG_FIFF_OFFSET] !=
1676 state->reg[MT2063_REG_FIFF_OFFSET] =
1679 mt2063_write(state,
1681 &state->
1694 status = mt2063_lockStatus(state);
1703 state->f_IF1_actual = state->AS_Data.f_LO1 - f_in;
1775 struct mt2063_state *state = fe->tuner_priv;
1786 state->rcvr_mode = MT2063_CABLE_QAM;
1789 status = mt2063_read(state, MT2063_REG_PART_REV,
1790 &state->reg[MT2063_REG_PART_REV], 1);
1797 switch (state->reg[MT2063_REG_PART_REV]) {
1812 state->reg[MT2063_REG_PART_REV]);
1817 status = mt2063_read(state, MT2063_REG_RSVD_3B,
1818 &state->reg[MT2063_REG_RSVD_3B], 1);
1821 if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) {
1823 state->reg[MT2063_REG_PART_REV],
1824 state->reg[MT2063_REG_RSVD_3B]);
1831 status = mt2063_write(state, MT2063_REG_LO2CQ_3, &all_resets, 1);
1836 /* def = (state->reg[PART_REV] == MT2063_B0) ? MT2063B0_defaults : MT2063B1_defaults; */
1837 switch (state->reg[MT2063_REG_PART_REV]) {
1858 status = mt2063_write(state, reg, &val, 1);
1868 status = mt2063_read(state,
1870 &state->
1872 FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6;
1878 status = mt2063_read(state,
1880 &state->reg[MT2063_REG_FIFFC], 1);
1885 status = mt2063_read(state,
1887 state->reg, MT2063_REG_END_REGS);
1891 /* Initialize the tuner state. */
1892 state->tuner_id = state->reg[MT2063_REG_PART_REV];
1893 state->AS_Data.f_ref = MT2063_REF_FREQ;
1894 state->AS_Data.f_if1_Center = (state->AS_Data.f_ref / 8) *
1895 ((u32) state->reg[MT2063_REG_FIFFC] + 640);
1896 state->AS_Data.f_if1_bw = MT2063_IF1_BW;
1897 state->AS_Data.f_out = 43750000UL;
1898 state->AS_Data.f_out_bw = 6750000UL;
1899 state->AS_Data.f_zif_bw = MT2063_ZIF_BW;
1900 state->AS_Data.f_LO1_Step = state->AS_Data.f_ref / 64;
1901 state->AS_Data.f_LO2_Step = MT2063_TUNE_STEP_SIZE;
1902 state->AS_Data.maxH1 = MT2063_MAX_HARMONICS_1;
1903 state->AS_Data.maxH2 = MT2063_MAX_HARMONICS_2;
1904 state->AS_Data.f_min_LO_Separation = MT2063_MIN_LO_SEP;
1905 state->AS_Data.f_if1_Request = state->AS_Data.f_if1_Center;
1906 state->AS_Data.f_LO1 = 2181000000UL;
1907 state->AS_Data.f_LO2 = 1486249786UL;
1908 state->f_IF1_actual = state->AS_Data.f_if1_Center;
1909 state->AS_Data.f_in = state->AS_Data.f_LO1 - state->f_IF1_actual;
1910 state->AS_Data.f_LO1_FracN_Avoid = MT2063_LO1_FRACN_AVOID;
1911 state->AS_Data.f_LO2_FracN_Avoid = MT2063_LO2_FRACN_AVOID;
1912 state->num_regs = MT2063_REG_END_REGS;
1913 state->AS_Data.avoidDECT = MT2063_AVOID_BOTH;
1914 state->ctfilt_sw = 0;
1916 state->CTFiltMax[0] = 69230000;
1917 state->CTFiltMax[1] = 105770000;
1918 state->CTFiltMax[2] = 140350000;
1919 state->CTFiltMax[3] = 177110000;
1920 state->CTFiltMax[4] = 212860000;
1921 state->CTFiltMax[5] = 241130000;
1922 state->CTFiltMax[6] = 274370000;
1923 state->CTFiltMax[7] = 309820000;
1924 state->CTFiltMax[8] = 342450000;
1925 state->CTFiltMax[9] = 378870000;
1926 state->CTFiltMax[10] = 416210000;
1927 state->CTFiltMax[11] = 456500000;
1928 state->CTFiltMax[12] = 495790000;
1929 state->CTFiltMax[13] = 534530000;
1930 state->CTFiltMax[14] = 572610000;
1931 state->CTFiltMax[15] = 598970000;
1932 state->CTFiltMax[16] = 635910000;
1933 state->CTFiltMax[17] = 672130000;
1934 state->CTFiltMax[18] = 714840000;
1935 state->CTFiltMax[19] = 739660000;
1936 state->CTFiltMax[20] = 770410000;
1937 state->CTFiltMax[21] = 814660000;
1938 state->CTFiltMax[22] = 846950000;
1939 state->CTFiltMax[23] = 867820000;
1940 state->CTFiltMax[24] = 915980000;
1941 state->CTFiltMax[25] = 947450000;
1942 state->CTFiltMax[26] = 983110000;
1943 state->CTFiltMax[27] = 1021630000;
1944 state->CTFiltMax[28] = 1061870000;
1945 state->CTFiltMax[29] = 1098330000;
1946 state->CTFiltMax[30] = 1138990000;
1953 state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A;
1954 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
1955 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
1960 status = mt2063_read(state, MT2063_REG_FIFFC,
1961 &state->reg[MT2063_REG_FIFFC], 1);
1965 fcu_osc = state->reg[MT2063_REG_FIFFC];
1967 state->reg[MT2063_REG_CTUNE_CTRL] = 0x00;
1968 status = mt2063_write(state, MT2063_REG_CTUNE_CTRL,
1969 &state->reg[MT2063_REG_CTUNE_CTRL], 1);
1975 state->CTFiltMax[i] = (state->CTFiltMax[i] / 768) * (fcu_osc + 640);
1977 status = MT2063_SoftwareShutdown(state, 1);
1980 status = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);
1984 state->init = true;
1991 struct mt2063_state *state = fe->tuner_priv;
1996 if (!state->init)
2000 status = mt2063_lockStatus(state);
2013 struct mt2063_state *state = fe->tuner_priv;
2018 kfree(state);
2024 struct mt2063_state *state = fe->tuner_priv;
2034 if (!state->init) {
2068 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
2069 state->AS_Data.f_out = if_mid;
2070 state->AS_Data.f_out_bw = ch_bw + 750000;
2071 status = MT2063_SetReceiverMode(state, rcvr_mode);
2078 status = MT2063_Tune(state, (params->frequency + (pict2chanb_vsb + (ch_bw / 2))));
2082 state->frequency = params->frequency;
2098 struct mt2063_state *state = fe->tuner_priv;
2106 if (!state->init) {
2140 state->AS_Data.f_LO2_Step = 125000; /* FIXME: probably 5000 for FM */
2141 state->AS_Data.f_out = if_mid;
2142 state->AS_Data.f_out_bw = ch_bw + 750000;
2143 status = MT2063_SetReceiverMode(state, rcvr_mode);
2150 status = MT2063_Tune(state, (c->frequency + (pict2chanb_vsb + (ch_bw / 2))));
2155 state->frequency = c->frequency;
2161 struct mt2063_state *state = fe->tuner_priv;
2165 if (!state->init)
2168 *freq = state->AS_Data.f_out;
2177 struct mt2063_state *state = fe->tuner_priv;
2181 if (!state->init)
2184 *bw = state->AS_Data.f_out_bw - 750000;
2212 struct mt2063_state *state = NULL;
2216 state = kzalloc(sizeof(struct mt2063_state), GFP_KERNEL);
2217 if (!state)
2220 state->config = config;
2221 state->i2c = i2c;
2222 state->frontend = fe;
2223 state->reference = config->refclock / 1000; /* kHz */
2224 fe->tuner_priv = state;
2239 struct mt2063_state *state = fe->tuner_priv;
2244 err = MT2063_SoftwareShutdown(state, 1);
2253 struct mt2063_state *state = fe->tuner_priv;
2258 err = MT2063_ClearPowerMaskBits(state, MT2063_ALL_SD);