Lines Matching defs:val
271 static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val)
280 status = mt2063_write(state, reg, &val, 1);
284 state->reg[reg] = val;
321 dprintk(2, "addr 0x%02x, ret = %d, val = 0x%02x\n",
1043 u8 val = 0;
1050 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1052 val)
1056 val);
1058 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1060 val)
1064 val);
1066 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1068 val)
1072 val);
1076 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1078 val)
1082 val);
1084 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */
1086 val)
1090 val);
1092 val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */
1094 val)
1098 val);
1102 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */
1104 val)
1108 val);
1110 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1112 val)
1116 val);
1118 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1120 val)
1124 val);
1128 val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */
1130 val)
1134 val);
1136 val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */
1138 val)
1142 val);
1144 val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */
1146 val)
1150 val);
1177 u8 val;
1187 val =
1192 if (state->reg[MT2063_REG_PD1_TGT] != val)
1193 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1198 u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) |
1200 if (state->reg[MT2063_REG_CTRL_2C] != val)
1201 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
1206 val =
1210 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
1212 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
1214 val =
1217 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1218 val =
1222 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1232 u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) |
1234 if (state->reg[MT2063_REG_LNA_OV] != val)
1235 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
1240 u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) |
1242 if (state->reg[MT2063_REG_LNA_TGT] != val)
1243 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1248 u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) |
1250 if (state->reg[MT2063_REG_RF_OV] != val)
1251 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
1256 u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) |
1258 if (state->reg[MT2063_REG_PD1_TGT] != val)
1259 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1264 u8 val = ACFIFMAX[Mode];
1265 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
1266 val = 5;
1267 val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) |
1268 (val & 0x1F);
1269 if (state->reg[MT2063_REG_FIF_OV] != val)
1270 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
1275 u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) |
1277 if (state->reg[MT2063_REG_PD2_TGT] != val)
1278 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
1283 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) |
1285 if (state->reg[MT2063_REG_LNA_TGT] != val)
1286 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
1291 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) |
1293 if (state->reg[MT2063_REG_PD1_TGT] != val)
1294 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
1522 u8 val;
1544 val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08);
1545 if (state->reg[MT2063_REG_CTUNE_CTRL] != val) {
1547 mt2063_setreg(state, MT2063_REG_CTUNE_CTRL, val);
1549 val = state->reg[MT2063_REG_CTUNE_OV];
1554 if (state->reg[MT2063_REG_CTUNE_OV] != val) {
1556 mt2063_setreg(state, MT2063_REG_CTUNE_OV, val);
1857 u8 val = *def++;
1858 status = mt2063_write(state, reg, &val, 1);