Lines Matching refs:ir
8 * Based on sun5i-ir.c:
20 #define SUNXI_IR_DEV "sunxi-ir"
61 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
109 struct sunxi_ir *ir = dev_id;
112 spin_lock(&ir->ir_lock);
114 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
117 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
123 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
127 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
130 ir->rc->rx_resolution;
131 ir_raw_event_store_with_filter(ir->rc, &rawir);
136 ir_raw_event_reset(ir->rc);
138 ir_raw_event_set_idle(ir->rc, true);
139 ir_raw_event_handle(ir->rc);
141 ir_raw_event_handle(ir->rc);
144 spin_unlock(&ir->ir_lock);
158 struct sunxi_ir *ir;
161 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
162 if (!ir)
171 spin_lock_init(&ir->ir_lock);
173 ir->fifo_size = quirks->fifo_size;
176 ir->apb_clk = devm_clk_get(dev, "apb");
177 if (IS_ERR(ir->apb_clk)) {
179 return PTR_ERR(ir->apb_clk);
181 ir->clk = devm_clk_get(dev, "ir");
182 if (IS_ERR(ir->clk)) {
183 dev_err(dev, "failed to get a ir clock.\n");
184 return PTR_ERR(ir->clk);
192 ir->rst = devm_reset_control_get_exclusive(dev, NULL);
193 if (IS_ERR(ir->rst))
194 return PTR_ERR(ir->rst);
195 ret = reset_control_deassert(ir->rst);
200 ret = clk_set_rate(ir->clk, b_clk_freq);
202 dev_err(dev, "set ir base clock failed!\n");
207 if (clk_prepare_enable(ir->apb_clk)) {
213 if (clk_prepare_enable(ir->clk)) {
221 ir->base = devm_ioremap_resource(dev, res);
222 if (IS_ERR(ir->base)) {
223 ret = PTR_ERR(ir->base);
227 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
228 if (!ir->rc) {
234 ir->rc->priv = ir;
235 ir->rc->device_name = SUNXI_IR_DEV;
236 ir->rc->input_phys = "sunxi-ir/input0";
237 ir->rc->input_id.bustype = BUS_HOST;
238 ir->rc->input_id.vendor = 0x0001;
239 ir->rc->input_id.product = 0x0001;
240 ir->rc->input_id.version = 0x0100;
241 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
242 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
243 ir->rc->dev.parent = dev;
244 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
246 ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
247 ir->rc->timeout = MS_TO_US(SUNXI_IR_TIMEOUT);
248 ir->rc->driver_name = SUNXI_IR_DEV;
250 ret = rc_register_device(ir->rc);
256 platform_set_drvdata(pdev, ir);
259 ir->irq = platform_get_irq(pdev, 0);
260 if (ir->irq < 0) {
261 ret = ir->irq;
265 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
272 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
276 ir->base + SUNXI_IR_CIR_REG);
279 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
282 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
289 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
290 ir->base + SUNXI_IR_RXINT_REG);
293 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
294 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
300 rc_free_device(ir->rc);
302 clk_disable_unprepare(ir->clk);
304 clk_disable_unprepare(ir->apb_clk);
306 reset_control_assert(ir->rst);
314 struct sunxi_ir *ir = platform_get_drvdata(pdev);
316 clk_disable_unprepare(ir->clk);
317 clk_disable_unprepare(ir->apb_clk);
318 reset_control_assert(ir->rst);
320 spin_lock_irqsave(&ir->ir_lock, flags);
322 writel(0, ir->base + SUNXI_IR_RXINT_REG);
324 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
326 writel(0, ir->base + SUNXI_IR_CTL_REG);
327 spin_unlock_irqrestore(&ir->ir_lock, flags);
329 rc_unregister_device(ir->rc);
350 .compatible = "allwinner,sun4i-a10-ir",
354 .compatible = "allwinner,sun5i-a13-ir",
358 .compatible = "allwinner,sun6i-a31-ir",