Lines Matching refs:dev
35 static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
37 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
38 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
42 static u8 ene_read_reg(struct ene_device *dev, u16 reg)
45 ene_set_reg_addr(dev, reg);
46 retval = inb(dev->hw_io + ENE_IO);
52 static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
55 ene_set_reg_addr(dev, reg);
56 outb(value, dev->hw_io + ENE_IO);
60 static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
63 ene_set_reg_addr(dev, reg);
64 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
68 static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
71 ene_set_reg_addr(dev, reg);
72 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
76 static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
80 ene_set_reg_mask(dev, reg, mask);
82 ene_clear_reg_mask(dev, reg, mask);
86 static int ene_hw_detect(struct ene_device *dev)
92 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
93 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
94 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
95 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
97 hw_revision = ene_read_reg(dev, ENE_ECHV);
98 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
100 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
101 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
104 dev->rx_period_adjust =
105 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
117 pr_notice("PLL freq = %d\n", dev->pll_freq);
125 dev->hw_revision = ENE_HW_C;
128 dev->hw_revision = ENE_HW_B;
131 dev->hw_revision = ENE_HW_D;
136 if (dev->hw_revision < ENE_HW_C)
139 fw_reg1 = ene_read_reg(dev, ENE_FW1);
140 fw_reg2 = ene_read_reg(dev, ENE_FW2);
144 dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
145 dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
146 dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
148 if (dev->hw_learning_and_tx_capable)
149 dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
153 if (dev->hw_learning_and_tx_capable) {
162 dev->hw_use_gpio_0a ? "40" : "0A");
164 if (dev->hw_fan_input)
168 if (!dev->hw_fan_input)
170 dev->hw_use_gpio_0a ? "0A" : "40");
172 if (dev->hw_extra_buffer)
178 static void ene_rx_setup_hw_buffer(struct ene_device *dev)
182 ene_rx_read_hw_pointer(dev);
183 dev->r_pointer = dev->w_pointer;
185 if (!dev->hw_extra_buffer) {
186 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
190 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
191 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
192 dev->extra_buf1_address = tmp;
194 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
196 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
197 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
198 dev->extra_buf2_address = tmp;
200 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
202 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
206 dev->extra_buf1_address, dev->extra_buf1_len);
208 dev->extra_buf2_address, dev->extra_buf2_len);
210 pr_notice("Total buffer len = %d\n", dev->buffer_len);
212 if (dev->buffer_len > 64 || dev->buffer_len < 16)
215 if (dev->extra_buf1_address > 0xFBFC ||
216 dev->extra_buf1_address < 0xEC00)
219 if (dev->extra_buf2_address > 0xFBFC ||
220 dev->extra_buf2_address < 0xEC00)
223 if (dev->r_pointer > dev->buffer_len)
226 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
230 dev->hw_extra_buffer = false;
231 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
236 static void ene_rx_restore_hw_buffer(struct ene_device *dev)
238 if (!dev->hw_extra_buffer)
241 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
242 dev->extra_buf1_address & 0xFF);
243 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
244 dev->extra_buf1_address >> 8);
245 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
247 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
248 dev->extra_buf2_address & 0xFF);
249 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
250 dev->extra_buf2_address >> 8);
251 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
252 dev->extra_buf2_len);
253 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
257 static void ene_rx_read_hw_pointer(struct ene_device *dev)
259 if (dev->hw_extra_buffer)
260 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
262 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
266 dev->w_pointer, dev->r_pointer);
270 static int ene_rx_get_sample_reg(struct ene_device *dev)
274 if (dev->r_pointer == dev->w_pointer) {
276 ene_rx_read_hw_pointer(dev);
279 if (dev->r_pointer == dev->w_pointer) {
280 dbg_verbose("RB: end of data at %d", dev->r_pointer);
284 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
285 r_pointer = dev->r_pointer;
287 dev->r_pointer++;
288 if (dev->r_pointer == dev->buffer_len)
289 dev->r_pointer = 0;
291 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
300 if (r_pointer < dev->extra_buf1_len) {
302 return dev->extra_buf1_address + r_pointer;
305 r_pointer -= dev->extra_buf1_len;
307 if (r_pointer < dev->extra_buf2_len) {
309 return dev->extra_buf2_address + r_pointer;
317 static void ene_rx_sense_carrier(struct ene_device *dev)
320 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
321 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
338 if (dev->carrier_detect_enabled) {
344 ir_raw_event_store(dev->rdev, &ev);
349 static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
351 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
356 static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
358 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
365 static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
367 if (!dev->hw_fan_input)
371 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
373 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
374 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
379 static void ene_rx_setup(struct ene_device *dev)
381 bool learning_mode = dev->learning_mode_enabled ||
382 dev->carrier_detect_enabled;
389 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
394 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
396 ene_write_reg(dev, ENE_CIRRLC_CFG,
400 if (dev->hw_revision < ENE_HW_C)
405 WARN_ON(!dev->hw_learning_and_tx_capable);
412 ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
413 dev->rx_fan_input_inuse = false;
416 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
419 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
420 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
421 dev->carrier_detect_enabled || debug);
423 if (dev->hw_fan_input)
424 dev->rx_fan_input_inuse = true;
426 ene_rx_select_input(dev, dev->hw_use_gpio_0a);
429 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
430 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
434 if (dev->rx_fan_input_inuse) {
435 dev->rdev->rx_resolution = ENE_FW_SAMPLE_PERIOD_FAN;
439 dev->rdev->min_timeout = dev->rdev->max_timeout =
443 dev->rdev->rx_resolution = sample_period;
450 dev->rdev->min_timeout = 127 * sample_period;
451 dev->rdev->max_timeout = 200000;
454 if (dev->hw_learning_and_tx_capable)
455 dev->rdev->tx_resolution = sample_period;
457 if (dev->rdev->timeout > dev->rdev->max_timeout)
458 dev->rdev->timeout = dev->rdev->max_timeout;
459 if (dev->rdev->timeout < dev->rdev->min_timeout)
460 dev->rdev->timeout = dev->rdev->min_timeout;
464 static void ene_rx_enable_hw(struct ene_device *dev)
469 if (dev->hw_revision < ENE_HW_C) {
470 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
471 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
473 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
476 reg_value |= (dev->irq & ENE_IRQ_MASK);
477 ene_write_reg(dev, ENE_IRQ, reg_value);
481 ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
482 ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
485 ene_irq_status(dev);
488 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
491 ir_raw_event_set_idle(dev->rdev, true);
495 static void ene_rx_enable(struct ene_device *dev)
497 ene_rx_enable_hw(dev);
498 dev->rx_enabled = true;
502 static void ene_rx_disable_hw(struct ene_device *dev)
505 ene_rx_enable_cir_engine(dev, false);
506 ene_rx_enable_fan_input(dev, false);
509 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
510 ir_raw_event_set_idle(dev->rdev, true);
514 static void ene_rx_disable(struct ene_device *dev)
516 ene_rx_disable_hw(dev);
517 dev->rx_enabled = false;
523 static void ene_rx_reset(struct ene_device *dev)
525 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
526 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
530 static void ene_tx_set_carrier(struct ene_device *dev)
535 spin_lock_irqsave(&dev->hw_lock, flags);
537 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
538 ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
540 if (!dev->tx_period)
543 BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
545 tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
550 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
553 ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
554 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
556 spin_unlock_irqrestore(&dev->hw_lock, flags);
560 static void ene_tx_set_transmitters(struct ene_device *dev)
564 spin_lock_irqsave(&dev->hw_lock, flags);
565 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
566 !!(dev->transmitter_mask & 0x01));
567 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
568 !!(dev->transmitter_mask & 0x02));
569 spin_unlock_irqrestore(&dev->hw_lock, flags);
573 static void ene_tx_enable(struct ene_device *dev)
575 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
576 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
578 dev->saved_conf1 = conf1;
591 if (dev->hw_revision == ENE_HW_C)
596 ene_write_reg(dev, ENE_CIRCFG, conf1);
600 static void ene_tx_disable(struct ene_device *dev)
602 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
603 dev->tx_buffer = NULL;
607 /* TX one sample - must be called with dev->hw_lock*/
608 static void ene_tx_sample(struct ene_device *dev)
612 bool pulse = dev->tx_sample_pulse;
614 if (!dev->tx_buffer) {
620 if (!dev->tx_sample) {
622 if (dev->tx_pos == dev->tx_len) {
623 if (!dev->tx_done) {
625 dev->tx_done = true;
629 ene_tx_disable(dev);
630 complete(&dev->tx_complete);
635 sample = dev->tx_buffer[dev->tx_pos++];
636 dev->tx_sample_pulse = !dev->tx_sample_pulse;
638 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
640 if (!dev->tx_sample)
641 dev->tx_sample = 1;
644 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
645 dev->tx_sample -= raw_tx;
652 ene_write_reg(dev,
653 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
655 dev->tx_reg = !dev->tx_reg;
659 mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
665 struct ene_device *dev = from_timer(dev, t, tx_sim_timer);
668 spin_lock_irqsave(&dev->hw_lock, flags);
669 ene_tx_sample(dev);
670 spin_unlock_irqrestore(&dev->hw_lock, flags);
675 static int ene_irq_status(struct ene_device *dev)
681 fw_flags2 = ene_read_reg(dev, ENE_FW2);
683 if (dev->hw_revision < ENE_HW_C) {
684 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
689 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
693 irq_status = ene_read_reg(dev, ENE_IRQ);
698 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
699 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
704 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
708 fw_flags1 = ene_read_reg(dev, ENE_FW1);
710 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
725 struct ene_device *dev = (struct ene_device *)data;
728 spin_lock_irqsave(&dev->hw_lock, flags);
731 ene_rx_read_hw_pointer(dev);
732 irq_status = ene_irq_status(dev);
741 if (!dev->hw_learning_and_tx_capable) {
745 ene_tx_sample(dev);
753 if (dev->hw_learning_and_tx_capable)
754 ene_rx_sense_carrier(dev);
758 if (!dev->hw_extra_buffer)
759 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
763 reg = ene_rx_get_sample_reg(dev);
769 hw_value = ene_read_reg(dev, reg);
771 if (dev->rx_fan_input_inuse) {
776 hw_value |= ene_read_reg(dev, reg + offset) << 8;
788 if (dev->rx_period_adjust) {
790 hw_sample /= (100 + dev->rx_period_adjust);
794 if (!dev->hw_extra_buffer && !hw_sample) {
795 dev->r_pointer = dev->w_pointer;
803 ir_raw_event_store_with_filter(dev->rdev, &ev);
806 ir_raw_event_handle(dev->rdev);
808 spin_unlock_irqrestore(&dev->hw_lock, flags);
813 static void ene_setup_default_settings(struct ene_device *dev)
815 dev->tx_period = 32;
816 dev->tx_duty_cycle = 50; /*%*/
817 dev->transmitter_mask = 0x03;
818 dev->learning_mode_enabled = learning_mode_force;
821 dev->rdev->timeout = MS_TO_US(150);
825 static void ene_setup_hw_settings(struct ene_device *dev)
827 if (dev->hw_learning_and_tx_capable) {
828 ene_tx_set_carrier(dev);
829 ene_tx_set_transmitters(dev);
832 ene_rx_setup(dev);
838 struct ene_device *dev = rdev->priv;
841 spin_lock_irqsave(&dev->hw_lock, flags);
842 ene_rx_enable(dev);
843 spin_unlock_irqrestore(&dev->hw_lock, flags);
850 struct ene_device *dev = rdev->priv;
852 spin_lock_irqsave(&dev->hw_lock, flags);
854 ene_rx_disable(dev);
855 spin_unlock_irqrestore(&dev->hw_lock, flags);
861 struct ene_device *dev = rdev->priv;
871 dev->transmitter_mask = tx_mask;
872 ene_tx_set_transmitters(dev);
879 struct ene_device *dev = rdev->priv;
895 dev->tx_period = period;
896 ene_tx_set_carrier(dev);
903 struct ene_device *dev = rdev->priv;
905 dev->tx_duty_cycle = duty_cycle;
906 ene_tx_set_carrier(dev);
913 struct ene_device *dev = rdev->priv;
915 if (enable == dev->learning_mode_enabled)
918 spin_lock_irqsave(&dev->hw_lock, flags);
919 dev->learning_mode_enabled = enable;
920 ene_rx_disable(dev);
921 ene_rx_setup(dev);
922 ene_rx_enable(dev);
923 spin_unlock_irqrestore(&dev->hw_lock, flags);
929 struct ene_device *dev = rdev->priv;
932 if (enable == dev->carrier_detect_enabled)
935 spin_lock_irqsave(&dev->hw_lock, flags);
936 dev->carrier_detect_enabled = enable;
937 ene_rx_disable(dev);
938 ene_rx_setup(dev);
939 ene_rx_enable(dev);
940 spin_unlock_irqrestore(&dev->hw_lock, flags);
947 struct ene_device *dev = rdev->priv;
950 ene_rx_reset(dev);
958 struct ene_device *dev = rdev->priv;
961 dev->tx_buffer = buf;
962 dev->tx_len = n;
963 dev->tx_pos = 0;
964 dev->tx_reg = 0;
965 dev->tx_done = 0;
966 dev->tx_sample = 0;
967 dev->tx_sample_pulse = false;
969 dbg("TX: %d samples", dev->tx_len);
971 spin_lock_irqsave(&dev->hw_lock, flags);
973 ene_tx_enable(dev);
976 ene_tx_sample(dev);
977 ene_tx_sample(dev);
979 spin_unlock_irqrestore(&dev->hw_lock, flags);
981 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
983 spin_lock_irqsave(&dev->hw_lock, flags);
984 ene_tx_disable(dev);
985 spin_unlock_irqrestore(&dev->hw_lock, flags);
996 struct ene_device *dev;
999 dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
1001 if (!dev || !rdev)
1008 dev->hw_io = -1;
1009 dev->irq = -1;
1018 spin_lock_init(&dev->hw_lock);
1020 dev->hw_io = pnp_port_start(pnp_dev, 0);
1021 dev->irq = pnp_irq(pnp_dev, 0);
1024 pnp_set_drvdata(pnp_dev, dev);
1025 dev->pnp_dev = pnp_dev;
1032 error = ene_hw_detect(dev);
1036 if (!dev->hw_learning_and_tx_capable && txsim) {
1037 dev->hw_learning_and_tx_capable = true;
1038 timer_setup(&dev->tx_sim_timer, ene_tx_irqsim, 0);
1042 if (!dev->hw_learning_and_tx_capable)
1046 rdev->priv = dev;
1054 if (dev->hw_learning_and_tx_capable) {
1056 init_completion(&dev->tx_complete);
1065 dev->rdev = rdev;
1067 ene_rx_setup_hw_buffer(dev);
1068 ene_setup_default_settings(dev);
1069 ene_setup_hw_settings(dev);
1071 device_set_wakeup_capable(&pnp_dev->dev, true);
1072 device_set_wakeup_enable(&pnp_dev->dev, true);
1080 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1084 if (request_irq(dev->irq, ene_isr,
1085 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1093 release_region(dev->hw_io, ENE_IO_SIZE);
1099 kfree(dev);
1106 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1109 rc_unregister_device(dev->rdev);
1110 del_timer_sync(&dev->tx_sim_timer);
1111 spin_lock_irqsave(&dev->hw_lock, flags);
1112 ene_rx_disable(dev);
1113 ene_rx_restore_hw_buffer(dev);
1114 spin_unlock_irqrestore(&dev->hw_lock, flags);
1116 free_irq(dev->irq, dev);
1117 release_region(dev->hw_io, ENE_IO_SIZE);
1118 kfree(dev);
1122 static void ene_enable_wake(struct ene_device *dev, bool enable)
1125 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1131 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1132 bool wake = device_may_wakeup(&dev->pnp_dev->dev);
1134 if (!wake && dev->rx_enabled)
1135 ene_rx_disable_hw(dev);
1137 ene_enable_wake(dev, wake);
1143 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1144 ene_setup_hw_settings(dev);
1146 if (dev->rx_enabled)
1147 ene_rx_enable(dev);
1149 ene_enable_wake(dev, false);
1156 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1157 ene_enable_wake(dev, true);