Lines Matching defs:jpu
190 * struct jpu - JPEG IP abstraction
204 struct jpu {
268 * @jpu: JPEG IP device for this context
277 struct jpu *jpu;
475 static u32 jpu_read(struct jpu *jpu, unsigned int reg)
477 return ioread32(jpu->regs + reg);
480 static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg)
482 iowrite32(val, jpu->regs + reg);
495 static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl,
500 jpu_write(jpu, tbl[i], reg + (i << 2));
503 static void jpu_set_qtbl(struct jpu *jpu, unsigned short quality)
505 jpu_set_tbl(jpu, JCQTBL(0), qtbl_lum[quality], QTBL_SIZE);
506 jpu_set_tbl(jpu, JCQTBL(1), qtbl_chr[quality], QTBL_SIZE);
509 static void jpu_set_htbl(struct jpu *jpu)
511 jpu_set_tbl(jpu, JCHTBD(0), hdctbl_lum, HDCTBL_SIZE);
512 jpu_set_tbl(jpu, JCHTBA(0), hactbl_lum, HACTBL_SIZE);
513 jpu_set_tbl(jpu, JCHTBD(1), hdctbl_chr, HDCTBL_SIZE);
514 jpu_set_tbl(jpu, JCHTBA(1), hactbl_chr, HACTBL_SIZE);
517 static int jpu_wait_reset(struct jpu *jpu)
523 while (jpu_read(jpu, JCCMD) & JCCMD_SRST) {
525 dev_err(jpu->dev, "timed out in reset\n");
534 static int jpu_reset(struct jpu *jpu)
536 jpu_write(jpu, JCCMD_SRST, JCCMD);
537 return jpu_wait_reset(jpu);
673 dev_name(ctx->jpu->dev));
782 dev_dbg(ctx->jpu->dev, "unknown format; set default format\n");
860 v4l2_err(&ctx->jpu->v4l2_dev, "%s queue busy\n", __func__);
898 spin_lock_irqsave(&ctx->jpu->lock, flags);
901 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
938 dev_err(ctx->jpu->dev, "src and dst formats do not match.\n");
1052 dev_err(ctx->jpu->dev, "%s field isn't supported\n",
1062 dev_err(ctx->jpu->dev,
1121 dev_err(ctx->jpu->dev, "incompatible or corrupted JPEG data\n");
1173 spin_lock_irqsave(&ctx->jpu->lock, flags);
1175 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1204 src_vq->lock = &ctx->jpu->mutex;
1205 src_vq->dev = ctx->jpu->v4l2_dev.dev;
1219 dst_vq->lock = &ctx->jpu->mutex;
1220 dst_vq->dev = ctx->jpu->v4l2_dev.dev;
1232 struct jpu *jpu = video_drvdata(file);
1246 ctx->jpu = jpu;
1247 ctx->encoder = vfd == &jpu->vfd_encoder;
1254 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpu->m2m_dev, ctx, jpu_queue_init);
1264 if (mutex_lock_interruptible(&jpu->mutex)) {
1269 if (jpu->ref_count == 0) {
1270 ret = clk_prepare_enable(jpu->clk);
1274 ret = jpu_reset(jpu);
1279 jpu->ref_count++;
1281 mutex_unlock(&jpu->mutex);
1285 clk_disable_unprepare(jpu->clk);
1287 mutex_unlock(&jpu->mutex);
1297 struct jpu *jpu = video_drvdata(file);
1306 mutex_lock(&jpu->mutex);
1307 if (--jpu->ref_count == 0)
1308 clk_disable_unprepare(jpu->clk);
1309 mutex_unlock(&jpu->mutex);
1334 spin_lock_irqsave(&ctx->jpu->lock, flags);
1344 jpu_write(ctx->jpu, JCCMD_SRST, JCCMD);
1346 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1348 v4l2_m2m_job_finish(ctx->jpu->m2m_dev, ctx->fh.m2m_ctx);
1354 struct jpu *jpu = ctx->jpu;
1363 if (jpu_wait_reset(jpu)) {
1368 spin_lock_irqsave(&ctx->jpu->lock, flags);
1370 jpu->curr = ctx;
1413 jpu_write(jpu, JCMOD_DSP_ENC | JCMOD_PCTR | redu |
1416 jpu_write(jpu, JIFECNT_SWAP_WB | inft, JIFECNT);
1417 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1418 jpu_write(jpu, JINTE_TRANSF_COMPL, JINTE);
1421 jpu_write(jpu, src_1_addr, JIFESYA1);
1422 jpu_write(jpu, src_2_addr, JIFESCA1);
1425 jpu_write(jpu, bpl, JIFESMW);
1427 jpu_write(jpu, (w >> 8) & JCSZ_MASK, JCHSZU);
1428 jpu_write(jpu, w & JCSZ_MASK, JCHSZD);
1430 jpu_write(jpu, (h >> 8) & JCSZ_MASK, JCVSZU);
1431 jpu_write(jpu, h & JCSZ_MASK, JCVSZD);
1433 jpu_write(jpu, w, JIFESHSZ);
1434 jpu_write(jpu, h, JIFESVSZ);
1436 jpu_write(jpu, dst_addr + JPU_JPEG_HDR_SIZE, JIFEDA1);
1438 jpu_write(jpu, 0 << JCQTN_SHIFT(1) | 1 << JCQTN_SHIFT(2) |
1441 jpu_write(jpu, 0 << JCHTN_AC_SHIFT(1) | 0 << JCHTN_DC_SHIFT(1) |
1446 jpu_set_qtbl(jpu, ctx->compr_quality);
1447 jpu_set_htbl(jpu);
1452 dev_err(ctx->jpu->dev,
1454 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1469 jpu_write(jpu, JCMOD_DSP_DEC | JCMOD_PCTR, JCMOD);
1470 jpu_write(jpu, JIFECNT_SWAP_WB, JIFECNT);
1471 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT);
1474 jpu_write(jpu, JINTE_TRANSF_COMPL | JINTE_ERR, JINTE);
1477 jpu_write(jpu, src_addr, JIFDSA1);
1478 jpu_write(jpu, dst_1_addr, JIFDDYA1);
1479 jpu_write(jpu, dst_2_addr, JIFDDCA1);
1481 jpu_write(jpu, bpl, JIFDDMW);
1485 jpu_write(jpu, JCCMD_JSRT, JCCMD);
1487 spin_unlock_irqrestore(&ctx->jpu->lock, flags);
1501 struct jpu *jpu = dev_id;
1506 int_status = jpu_read(jpu, JINTS);
1514 jpu_write(jpu, ~(int_status & JINTS_MASK), JINTS);
1516 jpu_write(jpu, JCCMD_JEND, JCCMD);
1518 spin_lock(&jpu->lock);
1524 curr_ctx = v4l2_m2m_get_curr_priv(jpu->m2m_dev);
1527 dev_err(jpu->dev, "no active context for m2m\n");
1536 unsigned long payload_size = jpu_read(jpu, JCDTCU) << 16
1537 | jpu_read(jpu, JCDTCM) << 8
1538 | jpu_read(jpu, JCDTCD);
1555 unsigned char error = jpu_read(jpu, JCDERR) & JCDERR_MASK;
1557 dev_dbg(jpu->dev, "processing error: %#X: %s\n", error,
1564 jpu->curr = NULL;
1567 jpu_write(jpu, JCCMD_SRST, JCCMD);
1568 spin_unlock(&jpu->lock);
1570 v4l2_m2m_job_finish(jpu->m2m_dev, curr_ctx->fh.m2m_ctx);
1575 spin_unlock(&jpu->lock);
1585 { .compatible = "renesas,jpu-r8a7790" }, /* H2 */
1586 { .compatible = "renesas,jpu-r8a7791" }, /* M2-W */
1587 { .compatible = "renesas,jpu-r8a7792" }, /* V2H */
1588 { .compatible = "renesas,jpu-r8a7793" }, /* M2-N */
1589 { .compatible = "renesas,rcar-gen2-jpu" },
1596 struct jpu *jpu;
1601 jpu = devm_kzalloc(&pdev->dev, sizeof(*jpu), GFP_KERNEL);
1602 if (!jpu)
1605 mutex_init(&jpu->mutex);
1606 spin_lock_init(&jpu->lock);
1607 jpu->dev = &pdev->dev;
1611 jpu->regs = devm_ioremap_resource(&pdev->dev, res);
1612 if (IS_ERR(jpu->regs))
1613 return PTR_ERR(jpu->regs);
1616 jpu->irq = ret = platform_get_irq(pdev, 0);
1622 ret = devm_request_irq(&pdev->dev, jpu->irq, jpu_irq_handler, 0,
1623 dev_name(&pdev->dev), jpu);
1625 dev_err(&pdev->dev, "cannot claim IRQ %d\n", jpu->irq);
1630 jpu->clk = devm_clk_get(&pdev->dev, NULL);
1631 if (IS_ERR(jpu->clk)) {
1633 return PTR_ERR(jpu->clk);
1637 ret = v4l2_device_register(&pdev->dev, &jpu->v4l2_dev);
1644 jpu->m2m_dev = v4l2_m2m_init(&jpu_m2m_ops);
1645 if (IS_ERR(jpu->m2m_dev)) {
1646 v4l2_err(&jpu->v4l2_dev, "Failed to init mem2mem device\n");
1647 ret = PTR_ERR(jpu->m2m_dev);
1655 strscpy(jpu->vfd_encoder.name, DRV_NAME, sizeof(jpu->vfd_encoder.name));
1656 jpu->vfd_encoder.fops = &jpu_fops;
1657 jpu->vfd_encoder.ioctl_ops = &jpu_ioctl_ops;
1658 jpu->vfd_encoder.minor = -1;
1659 jpu->vfd_encoder.release = video_device_release_empty;
1660 jpu->vfd_encoder.lock = &jpu->mutex;
1661 jpu->vfd_encoder.v4l2_dev = &jpu->v4l2_dev;
1662 jpu->vfd_encoder.vfl_dir = VFL_DIR_M2M;
1663 jpu->vfd_encoder.device_caps = V4L2_CAP_STREAMING |
1666 ret = video_register_device(&jpu->vfd_encoder, VFL_TYPE_VIDEO, -1);
1668 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1672 video_set_drvdata(&jpu->vfd_encoder, jpu);
1674 strscpy(jpu->vfd_decoder.name, DRV_NAME, sizeof(jpu->vfd_decoder.name));
1675 jpu->vfd_decoder.fops = &jpu_fops;
1676 jpu->vfd_decoder.ioctl_ops = &jpu_ioctl_ops;
1677 jpu->vfd_decoder.minor = -1;
1678 jpu->vfd_decoder.release = video_device_release_empty;
1679 jpu->vfd_decoder.lock = &jpu->mutex;
1680 jpu->vfd_decoder.v4l2_dev = &jpu->v4l2_dev;
1681 jpu->vfd_decoder.vfl_dir = VFL_DIR_M2M;
1682 jpu->vfd_decoder.device_caps = V4L2_CAP_STREAMING |
1685 ret = video_register_device(&jpu->vfd_decoder, VFL_TYPE_VIDEO, -1);
1687 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n");
1691 video_set_drvdata(&jpu->vfd_decoder, jpu);
1692 platform_set_drvdata(pdev, jpu);
1694 v4l2_info(&jpu->v4l2_dev, "encoder device registered as /dev/video%d\n",
1695 jpu->vfd_encoder.num);
1696 v4l2_info(&jpu->v4l2_dev, "decoder device registered as /dev/video%d\n",
1697 jpu->vfd_decoder.num);
1702 video_unregister_device(&jpu->vfd_encoder);
1705 v4l2_m2m_release(jpu->m2m_dev);
1708 v4l2_device_unregister(&jpu->v4l2_dev);
1715 struct jpu *jpu = platform_get_drvdata(pdev);
1717 video_unregister_device(&jpu->vfd_decoder);
1718 video_unregister_device(&jpu->vfd_encoder);
1719 v4l2_m2m_release(jpu->m2m_dev);
1720 v4l2_device_unregister(&jpu->v4l2_dev);
1728 struct jpu *jpu = dev_get_drvdata(dev);
1730 if (jpu->ref_count == 0)
1733 clk_disable_unprepare(jpu->clk);
1740 struct jpu *jpu = dev_get_drvdata(dev);
1742 if (jpu->ref_count == 0)
1745 clk_prepare_enable(jpu->clk);