Lines Matching refs:reg

27 	u32 reg;
30 	regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg);
36 		reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
44 		reg |= OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
62 	reg &= ~(OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK << shift);
63 	reg |= mode << shift;
65 	regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg);
130 	u32 reg;
139 		reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) &
142 		if (reg != power >> 2)
145 	} while ((reg != power >> 2) && (retry_count < 100));
170 	u32 reg;
214 	reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0);
216 	reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK |
219 	reg |= (DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1)
222 	reg |= (DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3)
225 	isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0);
227 	reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1);
229 	reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK |
232 	reg |= TCLK_TERM << ISPCSIPHY_REG1_TCLK_TERM_SHIFT;
233 	reg |= TCLK_MISS << ISPCSIPHY_REG1_TCLK_MISS_SHIFT;
234 	reg |= TCLK_SETTLE << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT;
236 	isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1);
239 	reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG);
242 		reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) |
244 		reg |= (lanes->data[i].pol <<
246 		reg |= (lanes->data[i].pos <<
250 	reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK |
252 	reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT;
253 	reg |= lanes->clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT;
255 	isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG);