Lines Matching refs:reg
47 u32 reg;
49 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
52 reg |= ISPCSI2_CTRL_FRAME;
54 reg &= ~ISPCSI2_CTRL_FRAME;
57 reg |= ISPCSI2_CTRL_VP_CLK_EN;
59 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
62 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
64 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
66 reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
67 reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
70 reg |= ISPCSI2_CTRL_ECC_EN;
72 reg &= ~ISPCSI2_CTRL_ECC_EN;
74 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
252 u32 reg;
254 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
262 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
263 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
267 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
270 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
283 u32 reg;
286 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
289 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
291 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
294 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
296 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
299 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
301 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
303 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
306 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
308 reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
309 reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
311 reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
312 reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
316 reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
318 reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
322 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
323 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
326 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
329 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
330 reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
331 reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
333 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
336 reg = isp_reg_readl(isp, csi2->regs1,
338 reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
339 reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
340 isp_reg_writel(isp, reg, csi2->regs1,
358 u32 reg;
360 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
363 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
365 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
368 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
370 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
373 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
375 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
377 reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
378 reg |= timing->stop_state_counter <<
381 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
412 u32 reg;
413 reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
440 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
442 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
444 reg = 0;
445 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
455 u32 reg;
456 reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
464 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
466 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
468 reg = 0;
470 isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
484 u32 reg;
497 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
499 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
517 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
519 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)