Lines Matching refs:cfg
21 u32 cfg;
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT);
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT);
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL);
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST;
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
73 u32 cfg, flip;
76 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
77 cfg &= ~(FIMC_REG_CITRGFMT_INROT90 | FIMC_REG_CITRGFMT_OUTROT90 |
87 cfg |= FIMC_REG_CITRGFMT_INROT90;
89 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
93 cfg |= fimc_hw_get_target_flip(ctx);
94 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
106 u32 cfg;
113 cfg = readl(dev->regs + FIMC_REG_CITRGFMT);
114 cfg &= ~(FIMC_REG_CITRGFMT_FMT_MASK | FIMC_REG_CITRGFMT_HSIZE_MASK |
119 cfg |= FIMC_REG_CITRGFMT_RGB;
122 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
126 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
128 cfg |= FIMC_REG_CITRGFMT_YCBCR422;
135 cfg |= (frame->height << 16) | frame->width;
137 cfg |= (frame->width << 16) | frame->height;
139 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
141 cfg = readl(dev->regs + FIMC_REG_CITAREA);
142 cfg &= ~FIMC_REG_CITAREA_MASK;
143 cfg |= (frame->width * frame->height);
144 writel(cfg, dev->regs + FIMC_REG_CITAREA);
151 u32 cfg;
153 cfg = (frame->f_height << 16) | frame->f_width;
154 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE);
157 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
159 cfg |= FIMC_REG_CIGCTRL_CSC_ITU601_709;
161 cfg &= ~FIMC_REG_CIGCTRL_CSC_ITU601_709;
162 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
172 u32 cfg;
175 cfg = (offset->y_v << 16) | offset->y_h;
176 writel(cfg, dev->regs + FIMC_REG_CIOYOFF);
178 cfg = (offset->cb_v << 16) | offset->cb_h;
179 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF);
181 cfg = (offset->cr_v << 16) | offset->cr_h;
182 writel(cfg, dev->regs + FIMC_REG_CIOCROFF);
187 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
189 cfg &= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK |
195 cfg |= ctx->out_order_1p;
197 cfg |= ctx->out_order_2p | FIMC_REG_CIOCTRL_YCBCR_2PLANE;
199 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
202 cfg |= FIMC_REG_CIOCTRL_RGB565;
204 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
206 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
208 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
213 u32 cfg = readl(dev->regs + FIMC_REG_ORGISIZE);
215 cfg |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
217 cfg &= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
218 writel(cfg, dev->regs + FIMC_REG_ORGISIZE);
223 u32 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
225 cfg |= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
227 cfg &= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE;
228 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
235 u32 cfg, shfactor;
238 cfg = shfactor << 28;
240 cfg |= (sc->pre_hratio << 16) | sc->pre_vratio;
241 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO);
243 cfg = (sc->pre_dst_width << 16) | sc->pre_dst_height;
244 writel(cfg, dev->regs + FIMC_REG_CISCPREDST);
254 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
256 cfg &= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE | FIMC_REG_CISCCTRL_CSCY2R_WIDE |
263 cfg |= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE |
267 cfg |= FIMC_REG_CISCCTRL_SCALERBYPASS;
270 cfg |= FIMC_REG_CISCCTRL_SCALEUP_H;
273 cfg |= FIMC_REG_CISCCTRL_SCALEUP_V;
276 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
281 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
284 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
287 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
296 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
298 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
300 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
302 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
305 cfg |= FIMC_REG_CISCCTRL_INTERLACE;
308 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
316 u32 cfg;
323 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
324 cfg &= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK |
328 cfg |= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
329 cfg |= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
330 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
332 cfg = readl(dev->regs + FIMC_REG_CIEXTEN);
334 cfg &= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK |
336 cfg |= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
337 cfg |= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
338 writel(cfg, dev->regs + FIMC_REG_CIEXTEN);
340 cfg |= FIMC_REG_CISCCTRL_MHRATIO(sc->main_hratio);
341 cfg |= FIMC_REG_CISCCTRL_MVRATIO(sc->main_vratio);
342 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
349 u32 cfg;
351 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
352 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE;
355 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
357 cfg &= FIMC_REG_CIIMGCPT_IMGCPTEN_SC;
359 cfg |= FIMC_REG_CIIMGCPT_IMGCPTEN;
360 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
365 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
366 cfg &= ~(FIMC_REG_CIIMGCPT_IMGCPTEN |
368 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT);
375 u32 cfg = 0;
378 cfg |= FIMC_REG_CIIMGEFF_IE_SC_AFTER |
380 cfg |= effect->type;
382 cfg |= (effect->pat_cb << 13) | effect->pat_cr;
385 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF);
392 u32 cfg;
397 cfg = readl(dev->regs + FIMC_REG_CIOCTRL);
398 cfg &= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK;
399 cfg |= (frame->alpha << 4);
400 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
425 u32 cfg;
428 cfg = (offset->y_v << 16) | offset->y_h;
429 writel(cfg, dev->regs + FIMC_REG_CIIYOFF);
431 cfg = (offset->cb_v << 16) | offset->cb_h;
432 writel(cfg, dev->regs + FIMC_REG_CIICBOFF);
434 cfg = (offset->cr_v << 16) | offset->cr_h;
435 writel(cfg, dev->regs + FIMC_REG_CIICROFF);
444 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
445 cfg &= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
452 cfg |= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
464 cfg |= ctx->in_order_2p | FIMC_REG_MSCTRL_C_INT_IN_2PLANE;
466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
471 cfg |= ctx->in_order_1p
474 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR422;
477 cfg |= ctx->in_order_2p
480 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
487 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
490 cfg = readl(dev->regs + FIMC_REG_CIDMAPARAM);
491 cfg &= ~FIMC_REG_CIDMAPARAM_TILE_MASK;
494 cfg |= FIMC_REG_CIDMAPARAM_R_64X32;
497 cfg |= FIMC_REG_CIDMAPARAM_W_64X32;
499 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM);
507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
515 writel(cfg, dev->regs + FIMC_REG_MSCTRL);
522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
531 u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
532 cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
533 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
539 cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
540 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
559 u32 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
561 cfg &= ~(FIMC_REG_CIGCTRL_INVPOLPCLK | FIMC_REG_CIGCTRL_INVPOLVSYNC |
566 cfg |= FIMC_REG_CIGCTRL_INVPOLPCLK;
569 cfg |= FIMC_REG_CIGCTRL_INVPOLVSYNC;
572 cfg |= FIMC_REG_CIGCTRL_INVPOLHREF;
575 cfg |= FIMC_REG_CIGCTRL_INVPOLHSYNC;
578 cfg |= FIMC_REG_CIGCTRL_INVPOLFIELD;
580 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
603 u32 bus_width, cfg = 0;
610 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
616 cfg = pix_desc[i].cisrcfmt;
631 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
633 cfg |= FIMC_REG_CISRCFMT_ITU601_16BIT;
638 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT;
646 cfg |= (f->o_width << 16) | f->o_height;
647 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT);
655 u32 cfg = readl(fimc->regs + FIMC_REG_CIWDOFST);
657 cfg &= ~(FIMC_REG_CIWDOFST_HOROFF_MASK | FIMC_REG_CIWDOFST_VEROFF_MASK);
658 cfg |= FIMC_REG_CIWDOFST_OFF_EN |
661 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST);
666 cfg = (hoff2 << 16) | voff2;
667 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2);
675 u32 cfg, tmp;
677 cfg = readl(fimc->regs + FIMC_REG_CIGCTRL);
680 cfg &= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK | FIMC_REG_CIGCTRL_SELCAM_ITU_A |
687 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI;
690 cfg |= FIMC_REG_CIGCTRL_SELCAM_MIPI_A;
700 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
714 cfg |= FIMC_REG_CIGCTRL_SELCAM_ITU_A;
716 cfg |= FIMC_REG_CIGCTRL_CAM_JPEG;
719 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
723 cfg |= FIMC_REG_CIGCTRL_CAMIF_SELWB;
733 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL);
740 u32 cfg = readl(dev->regs + FIMC_REG_CIGCTRL);
741 cfg |= FIMC_REG_CIGCTRL_IRQ_CLR;
742 writel(cfg, dev->regs + FIMC_REG_CIGCTRL);
747 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
749 cfg |= FIMC_REG_CISCCTRL_SCALERSTART;
751 cfg &= ~FIMC_REG_CISCCTRL_SCALERSTART;
752 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
757 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
759 cfg |= FIMC_REG_MSCTRL_ENVID;
761 cfg &= ~FIMC_REG_MSCTRL_ENVID;
762 writel(cfg, dev->regs + FIMC_REG_MSCTRL);