Lines Matching defs:value
287 u32 value;
289 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
290 value <<= VPIF_CH_LEN_SHIFT;
291 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
292 regw(value, vpifregs[channel_id].h_cfg);
294 value = (config->l1 & vpifregs[config_channel_id].len_mask);
295 value <<= VPIF_CH_LEN_SHIFT;
296 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
297 regw(value, vpifregs[channel_id].v_cfg_00);
299 value = (config->l5 & vpifregs[config_channel_id].len_mask);
300 value <<= VPIF_CH_LEN_SHIFT;
301 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
302 regw(value, vpifregs[channel_id].v_cfg_01);
304 value = (config->l9 & vpifregs[config_channel_id].len_mask);
305 value <<= VPIF_CH_LEN_SHIFT;
306 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
307 regw(value, vpifregs[channel_id].v_cfg_02);
309 value = (config->vsize & vpifregs[config_channel_id].len_mask);
310 regw(value, vpifregs[channel_id].v_cfg);
322 u32 value, ch_nip, reg;
356 value = regr(reg);
358 value &= ~(0x3u <<
360 value |= ((vpifparams->params.data_sz) <<
362 regw(value, reg);
398 u32 value;
400 value = 0x3F8 & (vbiparams->hstart0);
401 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
402 regw(value, vpifregs[channel_id].vanc0_strt);
404 value = 0x3F8 & (vbiparams->hstart1);
405 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
406 regw(value, vpifregs[channel_id].vanc1_strt);
408 value = 0x3F8 & (vbiparams->hsize0);
409 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
410 regw(value, vpifregs[channel_id].vanc0_size);
412 value = 0x3F8 & (vbiparams->hsize1);
413 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
414 regw(value, vpifregs[channel_id].vanc1_size);