Lines Matching defs:csi2rx
95 static void csi2rx_reset(struct csi2rx_priv *csi2rx)
98 csi2rx->base + CSI2RX_SOFT_RESET_REG);
102 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
105 static int csi2rx_start(struct csi2rx_priv *csi2rx)
112 ret = clk_prepare_enable(csi2rx->p_clk);
116 csi2rx_reset(csi2rx);
118 reg = csi2rx->num_lanes << 8;
119 for (i = 0; i < csi2rx->num_lanes; i++) {
120 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]);
121 set_bit(csi2rx->lanes[i], &lanes_used);
130 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) {
132 csi2rx->max_lanes);
137 writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG);
139 ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true);
153 for (i = 0; i < csi2rx->max_streams; i++) {
154 ret = clk_prepare_enable(csi2rx->pixel_clk[i]);
159 csi2rx->base + CSI2RX_STREAM_CFG_REG(i));
163 csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i));
166 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
169 ret = clk_prepare_enable(csi2rx->sys_clk);
173 clk_disable_unprepare(csi2rx->p_clk);
179 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]);
182 clk_disable_unprepare(csi2rx->p_clk);
187 static void csi2rx_stop(struct csi2rx_priv *csi2rx)
191 clk_prepare_enable(csi2rx->p_clk);
192 clk_disable_unprepare(csi2rx->sys_clk);
194 for (i = 0; i < csi2rx->max_streams; i++) {
195 writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
197 clk_disable_unprepare(csi2rx->pixel_clk[i]);
200 clk_disable_unprepare(csi2rx->p_clk);
202 if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))
203 dev_warn(csi2rx->dev, "Couldn't disable our subdev\n");
208 struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev);
211 mutex_lock(&csi2rx->lock);
218 if (!csi2rx->count) {
219 ret = csi2rx_start(csi2rx);
224 csi2rx->count++;
226 csi2rx->count--;
231 if (!csi2rx->count)
232 csi2rx_stop(csi2rx);
236 mutex_unlock(&csi2rx->lock);
253 struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev);
255 csi2rx->source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
258 if (csi2rx->source_pad < 0) {
259 dev_err(csi2rx->dev, "Couldn't find output pad for subdev %s\n",
261 return csi2rx->source_pad;
264 csi2rx->source_subdev = s_subdev;
266 dev_dbg(csi2rx->dev, "Bound %s pad: %d\n", s_subdev->name,
267 csi2rx->source_pad);
269 return media_create_pad_link(&csi2rx->source_subdev->entity,
270 csi2rx->source_pad,
271 &csi2rx->subdev.entity, 0,
280 static int csi2rx_get_resources(struct csi2rx_priv *csi2rx,
288 csi2rx->base = devm_ioremap_resource(&pdev->dev, res);
289 if (IS_ERR(csi2rx->base))
290 return PTR_ERR(csi2rx->base);
292 csi2rx->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
293 if (IS_ERR(csi2rx->sys_clk)) {
295 return PTR_ERR(csi2rx->sys_clk);
298 csi2rx->p_clk = devm_clk_get(&pdev->dev, "p_clk");
299 if (IS_ERR(csi2rx->p_clk)) {
301 return PTR_ERR(csi2rx->p_clk);
304 csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy");
305 if (IS_ERR(csi2rx->dphy)) {
307 return PTR_ERR(csi2rx->dphy);
314 if (csi2rx->dphy) {
319 clk_prepare_enable(csi2rx->p_clk);
320 dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG);
321 clk_disable_unprepare(csi2rx->p_clk);
323 csi2rx->max_lanes = dev_cfg & 7;
324 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) {
326 csi2rx->max_lanes);
330 csi2rx->max_streams = (dev_cfg >> 4) & 7;
331 if (csi2rx->max_streams > CSI2RX_STREAMS_MAX) {
333 csi2rx->max_streams);
337 csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false;
343 if (csi2rx->has_internal_dphy) {
348 for (i = 0; i < csi2rx->max_streams; i++) {
352 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name);
353 if (IS_ERR(csi2rx->pixel_clk[i])) {
355 return PTR_ERR(csi2rx->pixel_clk[i]);
362 static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx)
369 ep = of_graph_get_endpoint_by_regs(csi2rx->dev->of_node, 0, 0);
376 dev_err(csi2rx->dev, "Could not parse v4l2 endpoint\n");
382 dev_err(csi2rx->dev, "Unsupported media bus type: 0x%x\n",
388 memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
389 sizeof(csi2rx->lanes));
390 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes;
391 if (csi2rx->num_lanes > csi2rx->max_lanes) {
392 dev_err(csi2rx->dev, "Unsupported number of data-lanes: %d\n",
393 csi2rx->num_lanes);
398 csi2rx->asd.match.fwnode = fwnode_graph_get_remote_port_parent(fwh);
399 csi2rx->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
402 v4l2_async_notifier_init(&csi2rx->notifier);
404 ret = v4l2_async_notifier_add_subdev(&csi2rx->notifier, &csi2rx->asd);
406 fwnode_handle_put(csi2rx->asd.match.fwnode);
410 csi2rx->notifier.ops = &csi2rx_notifier_ops;
412 ret = v4l2_async_subdev_notifier_register(&csi2rx->subdev,
413 &csi2rx->notifier);
415 v4l2_async_notifier_cleanup(&csi2rx->notifier);
422 struct csi2rx_priv *csi2rx;
426 csi2rx = kzalloc(sizeof(*csi2rx), GFP_KERNEL);
427 if (!csi2rx)
429 platform_set_drvdata(pdev, csi2rx);
430 csi2rx->dev = &pdev->dev;
431 mutex_init(&csi2rx->lock);
433 ret = csi2rx_get_resources(csi2rx, pdev);
437 ret = csi2rx_parse_dt(csi2rx);
441 csi2rx->subdev.owner = THIS_MODULE;
442 csi2rx->subdev.dev = &pdev->dev;
443 v4l2_subdev_init(&csi2rx->subdev, &csi2rx_subdev_ops);
444 v4l2_set_subdevdata(&csi2rx->subdev, &pdev->dev);
445 snprintf(csi2rx->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.%s",
449 csi2rx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
450 csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
452 csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE;
454 ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX,
455 csi2rx->pads);
459 ret = v4l2_async_register_subdev(&csi2rx->subdev);
465 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams,
466 csi2rx->has_internal_dphy ? "internal" : "no");
471 v4l2_async_notifier_cleanup(&csi2rx->notifier);
473 kfree(csi2rx);
479 struct csi2rx_priv *csi2rx = platform_get_drvdata(pdev);
481 v4l2_async_unregister_subdev(&csi2rx->subdev);
482 kfree(csi2rx);
488 { .compatible = "cdns,csi2rx" },
498 .name = "cdns-csi2rx",