Lines Matching refs:input
180 static void tw5864_frame_interval_set(struct tw5864_input *input);
208 static int tw5864_input_std_get(struct tw5864_input *input,
211 struct tw5864_dev *dev = input->root;
212 u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr));
225 static int tw5864_enable_input(struct tw5864_input *input)
227 struct tw5864_dev *dev = input->root;
228 int nr = input->nr;
240 input->frame_seqno = 0;
241 input->frame_gop_seqno = 0;
242 input->h264_idr_pic_id = 0;
244 input->reg_dsp_qp = input->qp;
245 input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
246 input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
247 input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST
249 input->reg_dsp = nr /* channel id */
254 input->resolution = D1;
256 d1_height = (input->std == STD_NTSC) ? 480 : 576;
258 input->width = d1_width;
259 input->height = d1_height;
261 input->reg_interlacing = 0x4;
263 switch (input->resolution) {
266 frame_height_bus_value = input->height - 1;
270 input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;
271 input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
272 input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;
277 input->height /= 2;
278 input->width /= 2;
280 frame_height_bus_value = input->height * 2 - 1;
284 input->reg_dsp_codec |= TW5864_HD1_MAP_MD;
285 input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
291 input->height /= 4;
292 input->width /= 2;
294 frame_height_bus_value = input->height * 2 - 1;
298 input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
303 input->height /= 4;
304 input->width /= 4;
306 frame_height_bus_value = input->height * 2 - 1;
310 input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
316 /* analog input width / 4 */
321 tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);
322 tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);
328 input->width = 704;
334 ((input->width / 16) << 8) | (input->height / 16));
345 tw5864_frame_interval_set(input);
357 input->std == STD_NTSC ? 29 : 24);
364 input->enabled = 1;
370 void tw5864_request_encoded_frame(struct tw5864_input *input)
372 struct tw5864_dev *dev = input->root;
376 tw_writel(TW5864_EMU, input->reg_emu);
377 tw_writel(TW5864_INTERLACING, input->reg_interlacing);
378 tw_writel(TW5864_DSP, input->reg_dsp);
380 tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
381 tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
382 tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
387 if (input->frame_gop_seqno == 0) {
390 input->h264_idr_pic_id++;
391 input->h264_idr_pic_id &= TW5864_DSP_REF_FRM;
397 tw5864_prepare_frame_headers(input);
400 ((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) |
401 input->reg_dsp_qp);
404 2 * input->nr);
414 static int tw5864_disable_input(struct tw5864_input *input)
416 struct tw5864_dev *dev = input->root;
419 dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr);
422 input->enabled = 0;
429 struct tw5864_input *input = vb2_get_drv_priv(q);
432 ret = tw5864_enable_input(input);
436 while (!list_empty(&input->active)) {
437 struct tw5864_buf *buf = list_entry(input->active.next,
449 struct tw5864_input *input = vb2_get_drv_priv(q);
451 tw5864_disable_input(input);
453 spin_lock_irqsave(&input->slock, flags);
454 if (input->vb) {
455 vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
456 input->vb = NULL;
458 while (!list_empty(&input->active)) {
459 struct tw5864_buf *buf = list_entry(input->active.next,
465 spin_unlock_irqrestore(&input->slock, flags);
479 struct tw5864_input *input =
481 struct tw5864_dev *dev = input->root;
486 tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr),
490 tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr),
494 tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr),
498 tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr),
500 tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr),
504 input->gop = ctrl->val;
507 spin_lock_irqsave(&input->slock, flags);
508 input->qp = ctrl->val;
509 input->reg_dsp_qp = input->qp;
510 input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
511 input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
512 spin_unlock_irqrestore(&input->slock, flags);
515 memset(input->md_threshold_grid_values, ctrl->val,
516 sizeof(input->md_threshold_grid_values));
521 /* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */
522 memcpy(input->md_threshold_grid_values,
523 input->md_threshold_grid_ctrl->p_new.p_u16,
524 sizeof(input->md_threshold_grid_values));
533 struct tw5864_input *input = video_drvdata(file);
536 switch (input->std) {
558 struct tw5864_input *input = video_drvdata(file);
559 struct tw5864_dev *dev = input->root;
561 u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr));
562 u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr));
570 snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr);
602 struct tw5864_input *input = video_drvdata(file);
606 input->nr);
607 sprintf(cap->bus_info, "PCI:%s", pci_name(input->root->pci));
613 struct tw5864_input *input = video_drvdata(file);
617 ret = tw5864_input_std_get(input, &tw_std);
627 struct tw5864_input *input = video_drvdata(file);
629 *std = input->v4l2_std;
635 struct tw5864_input *input = video_drvdata(file);
636 struct tw5864_dev *dev = input->root;
638 input->v4l2_std = std;
639 input->std = tw5864_from_v4l2_std(std);
640 tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std);
669 static void tw5864_frame_interval_set(struct tw5864_input *input)
694 struct tw5864_dev *dev = input->root;
697 int std_max_fps = input->std == STD_NTSC ? 30 : 25;
699 for (shift = 0; shift < std_max_fps; shift += input->frame_interval)
702 tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
704 tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
708 static int tw5864_frameinterval_get(struct tw5864_input *input,
711 struct tw5864_dev *dev = input->root;
713 switch (input->std) {
725 input->std);
735 struct tw5864_input *input = video_drvdata(file);
744 fsize->discrete.height = input->std == STD_NTSC ? 480 : 576;
752 struct tw5864_input *input = video_drvdata(file);
754 int std_max_fps = input->std == STD_NTSC ? 30 : 25;
769 ret = tw5864_frameinterval_get(input, &frameinterval);
784 struct tw5864_input *input = video_drvdata(file);
790 ret = tw5864_frameinterval_get(input, &cp->timeperframe);
794 cp->timeperframe.numerator *= input->frame_interval;
804 struct tw5864_input *input = video_drvdata(file);
809 ret = tw5864_frameinterval_get(input, &time_base);
814 t->numerator = time_base.numerator * input->frame_interval;
822 input->frame_interval = t->numerator / time_base.numerator;
823 if (input->frame_interval < 1)
824 input->frame_interval = 1;
825 tw5864_frame_interval_set(input);
850 struct tw5864_input *input = video_drvdata(file);
851 struct tw5864_dev *dev = input->root;
872 struct tw5864_input *input = video_drvdata(file);
873 struct tw5864_dev *dev = input->root;
996 /* video input reset */
1098 static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)
1100 struct tw5864_dev *dev = input->root;
1102 struct v4l2_ctrl_handler *hdl = &input->hdl;
1104 mutex_init(&input->lock);
1105 spin_lock_init(&input->slock);
1108 INIT_LIST_HEAD(&input->active);
1109 input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1110 input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1111 input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1112 input->vidq.ops = &tw5864_video_qops;
1113 input->vidq.mem_ops = &vb2_dma_contig_memops;
1114 input->vidq.drv_priv = input;
1115 input->vidq.gfp_flags = 0;
1116 input->vidq.buf_struct_size = sizeof(struct tw5864_buf);
1117 input->vidq.lock = &input->lock;
1118 input->vidq.min_buffers_needed = 2;
1119 input->vidq.dev = &input->root->pci->dev;
1120 ret = vb2_queue_init(&input->vidq);
1124 input->vdev = tw5864_video_template;
1125 input->vdev.v4l2_dev = &input->root->v4l2_dev;
1126 input->vdev.lock = &input->lock;
1127 input->vdev.queue = &input->vidq;
1128 video_set_drvdata(&input->vdev, input);
1151 input->md_threshold_grid_ctrl =
1157 input->vdev.ctrl_handler = hdl;
1160 input->qp = QP_VALUE;
1161 input->gop = GOP_SIZE;
1162 input->frame_interval = 1;
1164 ret = video_register_device(&input->vdev, VFL_TYPE_VIDEO, video_nr);
1168 dev_info(&input->root->pci->dev, "Registered video device %s\n",
1169 video_device_node_name(&input->vdev));
1175 input->v4l2_std = V4L2_STD_NTSC_M;
1176 input->std = STD_NTSC;
1187 mutex_destroy(&input->lock);
1217 void tw5864_prepare_frame_headers(struct tw5864_input *input)
1219 struct tw5864_buf *vb = input->vb;
1225 spin_lock_irqsave(&input->slock, flags);
1226 if (list_empty(&input->active)) {
1227 spin_unlock_irqrestore(&input->slock, flags);
1228 input->vb = NULL;
1231 vb = list_first_entry(&input->active, struct tw5864_buf, list);
1233 spin_unlock_irqrestore(&input->slock, flags);
1254 if (input->frame_gop_seqno == 0)
1255 tw5864_h264_put_stream_header(&dst, &dst_space, input->qp,
1256 input->width, input->height);
1259 tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id,
1260 input->frame_gop_seqno,
1261 &input->tail_nb_bits, &input->tail);
1262 input->vb = vb;
1263 input->buf_cur_ptr = dst;
1264 input->buf_cur_space_left = dst_space;
1301 struct tw5864_input *input = frame->input;
1307 const u16 thresh = input->md_threshold_grid_values[i];
1366 struct tw5864_input *input = frame->input;
1367 struct tw5864_dev *dev = input->root;
1371 u8 *dst = input->buf_cur_ptr;
1387 spin_lock_irqsave(&input->slock, flags);
1388 vb = input->vb;
1389 input->vb = NULL;
1390 spin_unlock_irqrestore(&input->slock, flags);
1403 if (input->buf_cur_space_left < frame_len * 5 / 4) {
1406 input->buf_cur_space_left, frame_len);
1410 for (i = 0; i < 8 - input->tail_nb_bits; i++)
1414 dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);
1454 v4l2_event_queue(&input->vdev, &ev);