Lines Matching refs:mchip_dev
111 if (dma_set_mask(&meye.mchip_dev->dev, DMA_BIT_MASK(32)))
114 meye.mchip_ptable_toc = dma_alloc_coherent(&meye.mchip_dev->dev,
126 meye.mchip_ptable[i] = dma_alloc_coherent(&meye.mchip_dev->dev,
135 dma_free_coherent(&meye.mchip_dev->dev,
140 dma_free_coherent(&meye.mchip_dev->dev,
163 dma_free_coherent(&meye.mchip_dev->dev,
170 dma_free_coherent(&meye.mchip_dev->dev,
1015 sprintf(cap->bus_info, "PCI:%s", pci_name(meye.mchip_dev));
1541 pci_write_config_word(meye.mchip_dev, MCHIP_PCI_SOFTRESET_SET, 1);
1595 if (meye.mchip_dev != NULL) {
1606 meye.mchip_dev = pcidev;
1632 ret = pci_enable_device(meye.mchip_dev);
1639 mchip_adr = pci_resource_start(meye.mchip_dev,0);
1644 if (!request_mem_region(pci_resource_start(meye.mchip_dev, 0),
1645 pci_resource_len(meye.mchip_dev, 0),
1663 pci_write_config_byte(meye.mchip_dev, PCI_CACHE_LINE_SIZE, 8);
1664 pci_write_config_byte(meye.mchip_dev, PCI_LATENCY_TIMER, 64);
1666 pci_set_master(meye.mchip_dev);
1669 pci_write_config_word(meye.mchip_dev, MCHIP_PCI_SOFTRESET_SET, 1);
1719 meye.mchip_dev->revision, mchip_adr, meye.mchip_irq);
1729 release_mem_region(pci_resource_start(meye.mchip_dev, 0),
1730 pci_resource_len(meye.mchip_dev, 0));
1732 pci_disable_device(meye.mchip_dev);
1760 release_mem_region(pci_resource_start(meye.mchip_dev, 0),
1761 pci_resource_len(meye.mchip_dev, 0));
1763 pci_disable_device(meye.mchip_dev);