Lines Matching refs:value
236 * register value = (A/1e9 + B * UI) / COUNT_ACC
243 * depending whether the register minimum or maximum value is
263 * shift for keeping value range suitable for 32-bit integer arithmetic
283 /* max value of a is 95 */
289 /* Calculate the the delay value for termination enable of clock lane HS Rx */
315 if (!qm.value) {
319 freq = qm.value;
338 dev_dbg(dev, "freq ct value is %d\n", timing->clk_termen);
339 dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle);
340 dev_dbg(dev, "freq dt value is %d\n", timing->dat_termen);
341 dev_dbg(dev, "freq ds value is %d\n", timing->dat_settle);
512 u32 value;
524 value, value & CIO2_CDMAC0_DMA_HALTED,