Lines Matching refs:pd
128 struct dt3155_priv *pd = vb2_get_drv_priv(vq);
129 unsigned size = pd->width * pd->height;
142 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
144 vb2_set_plane_payload(vb, 0, pd->width * pd->height);
150 struct dt3155_priv *pd = vb2_get_drv_priv(q);
151 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
154 pd->sequence = 0;
156 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
157 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
158 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
159 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
162 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
165 pd->regs + CSR1);
166 wait_i2c_reg(pd->regs);
167 write_i2c_reg(pd->regs, CONFIG, pd->config);
168 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
169 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
172 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
178 struct dt3155_priv *pd = vb2_get_drv_priv(q);
181 spin_lock_irq(&pd->lock);
183 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
185 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
187 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
188 spin_unlock_irq(&pd->lock);
197 spin_lock_irq(&pd->lock);
198 if (pd->curr_buf) {
199 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
200 pd->curr_buf = NULL;
203 while (!list_empty(&pd->dmaq)) {
204 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
208 spin_unlock_irq(&pd->lock);
214 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
216 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */
217 spin_lock_irq(&pd->lock);
218 if (pd->curr_buf)
219 list_add_tail(&vb->done_entry, &pd->dmaq);
221 pd->curr_buf = vbuf;
222 spin_unlock_irq(&pd->lock);
295 struct dt3155_priv *pd = video_drvdata(filp);
299 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
314 struct dt3155_priv *pd = video_drvdata(filp);
316 f->fmt.pix.width = pd->width;
317 f->fmt.pix.height = pd->height;
328 struct dt3155_priv *pd = video_drvdata(filp);
330 *norm = pd->std;
336 struct dt3155_priv *pd = video_drvdata(filp);
338 if (pd->std == norm)
340 if (vb2_is_busy(&pd->vidq))
342 pd->std = norm;
343 if (pd->std & V4L2_STD_525_60) {
344 pd->csr2 = VT_60HZ;
345 pd->width = 640;
346 pd->height = 480;
348 pd->csr2 = VT_50HZ;
349 pd->width = 768;
350 pd->height = 576;
373 struct dt3155_priv *pd = video_drvdata(filp);
375 *i = pd->input;
381 struct dt3155_priv *pd = video_drvdata(filp);
385 pd->input = i;
386 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
387 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
412 static int dt3155_init_board(struct dt3155_priv *pd)
414 struct pci_dev *pdev = pd->pdev;
422 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
426 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
427 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
428 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
429 iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
430 iowrite32(0x00000103, pd->regs + XFER_MODE);
431 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
432 iowrite32(0, pd->regs + INT_CSR);
433 iowrite32(1, pd->regs + EVEN_FLD_MASK);
434 iowrite32(1, pd->regs + ODD_FLD_MASK);
435 iowrite32(0, pd->regs + MASK_LENGTH);
436 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
437 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
440 read_i2c_reg(pd->regs, DT_ID, &tmp);
445 write_i2c_reg(pd->regs, AD_ADDR, 0);
447 write_i2c_reg(pd->regs, AD_LUT, i);
451 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
452 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
453 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
454 write_i2c_reg(pd->regs, AD_CMD, 34);
455 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
456 write_i2c_reg(pd->regs, AD_CMD, 0);
459 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
461 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
462 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
464 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
466 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
467 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
469 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
472 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
473 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
477 pd->regs + INT_CSR);
496 struct dt3155_priv *pd;
501 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
502 if (!pd)
505 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
508 pd->vdev = dt3155_vdev;
509 pd->vdev.v4l2_dev = &pd->v4l2_dev;
510 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */
511 pd->pdev = pdev;
512 pd->std = V4L2_STD_625_50;
513 pd->csr2 = VT_50HZ;
514 pd->width = 768;
515 pd->height = 576;
516 INIT_LIST_HEAD(&pd->dmaq);
517 mutex_init(&pd->mux);
518 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
519 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
520 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
521 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
522 pd->vidq.ops = &q_ops;
523 pd->vidq.mem_ops = &vb2_dma_contig_memops;
524 pd->vidq.drv_priv = pd;
525 pd->vidq.min_buffers_needed = 2;
526 pd->vidq.gfp_flags = GFP_DMA32;
527 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
528 pd->vidq.dev = &pdev->dev;
529 pd->vdev.queue = &pd->vidq;
530 err = vb2_queue_init(&pd->vidq);
533 spin_lock_init(&pd->lock);
534 pd->config = ACQ_MODE_EVEN;
541 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
542 if (!pd->regs) {
546 err = dt3155_init_board(pd);
549 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
550 IRQF_SHARED, DT3155_NAME, pd);
553 err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
556 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
560 free_irq(pd->pdev->irq, pd);
562 pci_iounmap(pdev, pd->regs);
568 v4l2_device_unregister(&pd->v4l2_dev);
575 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
578 vb2_video_unregister_device(&pd->vdev);
579 free_irq(pd->pdev->irq, pd);
580 v4l2_device_unregister(&pd->v4l2_dev);
581 pci_iounmap(pdev, pd->regs);