Lines Matching defs:ts1
2134 struct cx23885_tsport *ts1 = &dev->ts1;
2197 ts1->gen_ctrl_val = 0x4; /* Parallel */
2198 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2199 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2214 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2215 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2216 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2222 ts1->gen_ctrl_val = 0x10e;
2223 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2224 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2227 ts1->vld_misc_val = 0x2000;
2228 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
2237 ts1->gen_ctrl_val = 0x4; /* Parallel */
2238 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2239 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2249 ts1->gen_ctrl_val = 0x5; /* Parallel */
2250 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2251 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2256 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2257 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2258 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2265 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2266 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2267 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2276 ts1->gen_ctrl_val = 0x5; /* Parallel */
2277 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2278 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2281 ts1->gen_ctrl_val = 0x5; /* Parallel */
2282 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2283 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2289 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2290 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2291 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2297 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2298 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2299 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2303 ts1->gen_ctrl_val = 0x5; /* Parallel */
2304 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2305 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2311 ts1->gen_ctrl_val = 0x5; /* Parallel */
2312 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2313 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2320 ts1->gen_ctrl_val = 0x5; /* Parallel */
2321 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2322 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
2332 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
2333 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
2334 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;