Lines Matching refs:cx
87 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
95 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
104 cx18_setup_page(cx, i);
107 cx18_raw_writel(cx, *src, dst);
108 if (cx18_raw_readl(cx, dst) != *src) {
111 cx18_setup_page(cx, 0);
118 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
122 cx18_setup_page(cx, SCB_OFFSET);
126 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx,
139 if (request_firmware(&fw, fn, &cx->pci_dev->dev)) {
142 cx18_setup_page(cx, 0);
173 cx18_setup_page(cx, seghdr.addr + i);
176 cx18_raw_writel(cx, src[(offset + j) / 4],
178 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
183 cx18_setup_page(cx, 0);
190 if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
195 cx18_setup_page(cx, 0);
199 void cx18_halt_firmware(struct cx18 *cx)
202 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
204 cx18_write_reg_expect(cx, 0x00020002, CX18_ADEC_CONTROL,
208 void cx18_init_power(struct cx18 *cx, int lowpwr)
212 cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
215 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
257 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
258 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
261 cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
262 cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
263 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
268 cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
269 cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
271 cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
275 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
276 cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
277 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
295 cx18_write_reg_expect(cx, 0xFFFF0020, CX18_CLOCK_SELECT1,
297 cx18_write_reg_expect(cx, 0xFFFF0004, CX18_CLOCK_SELECT2,
301 cx18_write_reg_expect(cx, 0x00060004, CX18_CLOCK_SELECT1,
303 cx18_write_reg_expect(cx, 0x00060006, CX18_CLOCK_SELECT2,
307 cx18_write_reg_expect(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1,
309 cx18_write_reg_expect(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2,
311 cx18_write_reg_expect(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1,
313 cx18_write_reg_expect(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2,
317 void cx18_init_memory(struct cx18 *cx)
320 cx18_write_reg_expect(cx, 0x00010000, CX18_DDR_SOFT_RESET,
324 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
328 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
329 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
330 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
335 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
336 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
340 cx18_write_reg_expect(cx, 0x00020000, CX18_DDR_SOFT_RESET,
345 cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
347 cx18_write_reg_expect(cx, 0x00010001, CX18_REG_BUS_TIMEOUT_EN,
350 cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
351 cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
353 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
354 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
355 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
356 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
357 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
358 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
359 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
360 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
361 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
362 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
368 int cx18_firmware_init(struct cx18 *cx)
375 cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
378 cx18_write_reg_expect(cx, 0x000F000F, CX18_PROC_SOFT_RESET,
384 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) == 0) {
389 cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
390 cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
392 sz = load_cpu_fw_direct(CX18_CPU_FIRMWARE, cx->enc_mem, cx);
397 cx18_init_scb(cx);
400 sz = load_apu_fw_direct(CX18_APU_FIRMWARE, cx->enc_mem, cx,
406 cx18_write_reg_expect(cx, 0x00080000, CX18_PROC_SOFT_RESET,
411 retries < 50 && (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1;
418 (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 1) == 1) {
432 cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
435 sz = cx18_vapi_result(cx, api_args, CX18_CPU_DEBUG_PEEK32, 1, 0);
440 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);