Lines Matching refs:bridge
3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
218 static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)
220 struct i2c_client *client = bridge->i2c_client;
248 static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)
250 struct i2c_client *client = bridge->i2c_client;
274 static int mipid02_get_regulators(struct mipid02_dev *bridge)
279 bridge->supplies[i].supply = mipid02_supply_name[i];
281 return devm_regulator_bulk_get(&bridge->i2c_client->dev,
283 bridge->supplies);
286 static void mipid02_apply_reset(struct mipid02_dev *bridge)
288 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
290 gpiod_set_value_cansleep(bridge->reset_gpio, 1);
292 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
296 static int mipid02_set_power_on(struct mipid02_dev *bridge)
298 struct i2c_client *client = bridge->i2c_client;
301 ret = clk_prepare_enable(bridge->xclk);
308 bridge->supplies);
315 if (bridge->reset_gpio) {
317 mipid02_apply_reset(bridge);
326 clk_disable_unprepare(bridge->xclk);
330 static void mipid02_set_power_off(struct mipid02_dev *bridge)
332 regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
333 clk_disable_unprepare(bridge->xclk);
336 static int mipid02_detect(struct mipid02_dev *bridge)
344 return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, ®);
347 static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,
366 static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,
369 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
372 u32 bpp = bpp_from_code(bridge->fmt.code);
387 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)
389 struct i2c_client *client = bridge->i2c_client;
390 struct v4l2_subdev *subdev = bridge->s_subdev;
393 link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);
395 link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,
404 bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2;
409 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
411 struct i2c_client *client = bridge->i2c_client;
412 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
420 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
425 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
438 bridge->r.data_lane0_reg1 = 1 << 1;
439 bridge->r.data_lane0_reg1 |= DATA_ENABLE;
444 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
453 bridge->r.data_lane1_reg1 = 1 << 1;
454 bridge->r.data_lane1_reg1 |= DATA_ENABLE;
459 static int mipid02_configure_from_rx(struct mipid02_dev *bridge)
461 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
467 ret = mipid02_configure_clk_lane(bridge);
471 ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
476 ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
481 bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
482 bridge->r.mode_reg1 |= (nb - 1) << 1;
484 return mipid02_configure_from_rx_speed(bridge);
487 static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
489 struct v4l2_fwnode_endpoint *ep = &bridge->tx;
491 bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
492 bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
493 bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
495 bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
497 bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
502 static int mipid02_configure_from_code(struct mipid02_dev *bridge)
506 bridge->r.data_id_rreg = 0;
508 if (bridge->fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {
509 bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
511 data_type = data_type_from_code(bridge->fmt.code);
514 bridge->r.data_id_rreg = data_type;
520 static int mipid02_stream_disable(struct mipid02_dev *bridge)
522 struct i2c_client *client = bridge->i2c_client;
526 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);
529 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);
532 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);
542 static int mipid02_stream_enable(struct mipid02_dev *bridge)
544 struct i2c_client *client = bridge->i2c_client;
547 if (!bridge->s_subdev)
550 memset(&bridge->r, 0, sizeof(bridge->r));
552 ret = mipid02_configure_from_rx(bridge);
555 ret = mipid02_configure_from_tx(bridge);
558 ret = mipid02_configure_from_code(bridge);
563 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,
564 bridge->r.clk_lane_reg1);
567 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);
570 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,
571 bridge->r.data_lane0_reg1);
574 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,
578 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,
579 bridge->r.data_lane1_reg1);
582 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,
586 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,
587 MODE_NO_BYPASS | bridge->r.mode_reg1);
590 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,
591 bridge->r.mode_reg2);
594 ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,
595 bridge->r.data_id_rreg);
598 ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,
599 bridge->r.data_selection_ctrl);
602 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,
603 bridge->r.pix_width_ctrl);
606 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,
607 bridge->r.pix_width_ctrl_emb);
615 mipid02_stream_disable(bridge);
622 struct mipid02_dev *bridge = to_mipid02_dev(sd);
623 struct i2c_client *client = bridge->i2c_client;
627 enable, bridge->streaming);
628 mutex_lock(&bridge->lock);
630 if (bridge->streaming == enable)
633 ret = enable ? mipid02_stream_enable(bridge) :
634 mipid02_stream_disable(bridge);
636 bridge->streaming = enable;
640 bridge->streaming, ret);
641 mutex_unlock(&bridge->lock);
650 struct mipid02_dev *bridge = to_mipid02_dev(sd);
662 code->code = serial_to_parallel_code(bridge->fmt.code);
678 struct mipid02_dev *bridge = to_mipid02_dev(sd);
679 struct i2c_client *client = bridge->i2c_client;
691 fmt = v4l2_subdev_get_try_format(&bridge->sd, cfg, format->pad);
693 fmt = &bridge->fmt;
695 mutex_lock(&bridge->lock);
702 mutex_unlock(&bridge->lock);
711 struct mipid02_dev *bridge = to_mipid02_dev(sd);
714 format->format = bridge->fmt;
729 struct mipid02_dev *bridge = to_mipid02_dev(sd);
737 fmt = &bridge->fmt;
746 struct mipid02_dev *bridge = to_mipid02_dev(sd);
747 struct i2c_client *client = bridge->i2c_client;
758 mutex_lock(&bridge->lock);
760 if (bridge->streaming) {
771 mutex_unlock(&bridge->lock);
799 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
800 struct i2c_client *client = bridge->i2c_client;
816 &bridge->sd.entity, 0,
824 bridge->s_subdev = s_subdev;
833 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
835 bridge->s_subdev = NULL;
843 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
846 struct i2c_client *client = bridge->i2c_client;
851 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
875 bridge->rx = ep;
878 bridge->asd.match.fwnode =
880 bridge->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
883 v4l2_async_notifier_init(&bridge->notifier);
884 ret = v4l2_async_notifier_add_subdev(&bridge->notifier, &bridge->asd);
888 fwnode_handle_put(bridge->asd.match.fwnode);
891 bridge->notifier.ops = &mipid02_notifier_ops;
893 ret = v4l2_async_subdev_notifier_register(&bridge->sd,
894 &bridge->notifier);
896 v4l2_async_notifier_cleanup(&bridge->notifier);
907 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
910 struct i2c_client *client = bridge->i2c_client;
915 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
930 bridge->tx = ep;
944 struct mipid02_dev *bridge;
948 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
949 if (!bridge)
952 init_format(&bridge->fmt);
954 bridge->i2c_client = client;
955 v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
958 bridge->xclk = devm_clk_get(dev, "xclk");
959 if (IS_ERR(bridge->xclk)) {
961 return PTR_ERR(bridge->xclk);
964 clk_freq = clk_get_rate(bridge->xclk);
971 bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
974 if (IS_ERR(bridge->reset_gpio)) {
976 return PTR_ERR(bridge->reset_gpio);
979 ret = mipid02_get_regulators(bridge);
985 mutex_init(&bridge->lock);
986 bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
987 bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
988 bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
989 bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
990 bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
991 bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
992 ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
993 bridge->pad);
1000 ret = mipid02_set_power_on(bridge);
1004 ret = mipid02_detect(bridge);
1010 ret = mipid02_parse_tx_ep(bridge);
1016 ret = mipid02_parse_rx_ep(bridge);
1022 ret = v4l2_async_register_subdev(&bridge->sd);
1034 v4l2_async_notifier_unregister(&bridge->notifier);
1035 v4l2_async_notifier_cleanup(&bridge->notifier);
1037 mipid02_set_power_off(bridge);
1039 media_entity_cleanup(&bridge->sd.entity);
1041 mutex_destroy(&bridge->lock);
1049 struct mipid02_dev *bridge = to_mipid02_dev(sd);
1051 v4l2_async_notifier_unregister(&bridge->notifier);
1052 v4l2_async_notifier_cleanup(&bridge->notifier);
1053 v4l2_async_unregister_subdev(&bridge->sd);
1054 mipid02_set_power_off(bridge);
1055 media_entity_cleanup(&bridge->sd.entity);
1056 mutex_destroy(&bridge->lock);
1079 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");