Lines Matching refs:vt
61 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
62 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
73 dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
74 dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
126 dev, pll->vt.sys_clk_freq_hz,
127 limits->vt.min_sys_clk_freq_hz,
128 limits->vt.max_sys_clk_freq_hz,
132 dev, pll->vt.pix_clk_freq_hz,
133 limits->vt.min_pix_clk_freq_hz,
134 limits->vt.max_pix_clk_freq_hz,
283 * Find absolute limits for the factor of vt divider.
291 /* Find smallest and biggest allowed vt divisor. */
295 limits->vt.max_pix_clk_freq_hz));
299 limits->vt.min_pix_clk_div
300 * limits->vt.min_sys_clk_div);
303 max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
307 limits->vt.min_pix_clk_freq_hz));
315 min_sys_div = limits->vt.min_sys_clk_div;
319 limits->vt.max_pix_clk_div));
323 / limits->vt.max_sys_clk_freq_hz);
328 max_sys_div = limits->vt.max_sys_clk_div;
332 limits->vt.min_pix_clk_div));
336 limits->vt.min_pix_clk_freq_hz));
351 if (pix_div < limits->vt.min_pix_clk_div
352 || pix_div > limits->vt.max_pix_clk_div) {
356 limits->vt.min_pix_clk_div,
357 limits->vt.max_pix_clk_div);
370 pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
371 pll->vt.pix_clk_div = best_pix_div;
373 pll->vt.sys_clk_freq_hz =
374 pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
375 pll->vt.pix_clk_freq_hz =
376 pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
381 pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
405 op_limits = &limits->vt;
406 op_pll = &pll->vt;