Lines Matching defs:ov2740_write_reg
393 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
420 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
437 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
445 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
454 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
482 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
492 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
497 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
625 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
637 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
956 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
964 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
971 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
991 ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
993 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
994 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);