Lines Matching refs:xvclk
85 struct clk *xvclk;
105 /* PLL settings bases on 24M xvclk */
398 ret = clk_prepare_enable(ov2685->xvclk);
400 dev_err(dev, "Failed to enable xvclk\n");
414 /* 8192 xvclk cycles prior to the first SCCB transaction */
430 clk_disable_unprepare(ov2685->xvclk);
437 /* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
441 clk_disable_unprepare(ov2685->xvclk);
727 ov2685->xvclk = devm_clk_get(dev, "xvclk");
728 if (IS_ERR(ov2685->xvclk)) {
729 dev_err(dev, "Failed to get xvclk\n");
732 ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);
734 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
737 if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
738 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");