Lines Matching defs:imx290
65 struct imx290 {
290 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
292 if (imx290->nlanes == 2)
298 static inline int imx290_link_freqs_num(const struct imx290 *imx290)
300 if (imx290->nlanes == 2)
345 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
347 if (imx290->nlanes == 2)
353 static inline int imx290_modes_num(const struct imx290 *imx290)
355 if (imx290->nlanes == 2)
361 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
363 return container_of(_sd, struct imx290, sd);
366 static inline int imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
371 ret = regmap_read(imx290->regmap, addr, ®val);
373 dev_err(imx290->dev, "I2C read failed for addr: %x\n", addr);
382 static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
386 ret = regmap_write(imx290->regmap, addr, value);
388 dev_err(imx290->dev, "I2C write failed for addr: %x\n", addr);
395 static int imx290_set_register_array(struct imx290 *imx290,
403 ret = imx290_write_reg(imx290, settings->reg, settings->val);
414 static int imx290_write_buffered_reg(struct imx290 *imx290, u16 address_low,
420 ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);
422 dev_err(imx290->dev, "Error setting hold register\n");
427 ret = imx290_write_reg(imx290, address_low + i,
430 dev_err(imx290->dev, "Error writing buffered registers\n");
435 ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);
437 dev_err(imx290->dev, "Error setting hold register\n");
444 static int imx290_set_gain(struct imx290 *imx290, u32 value)
448 ret = imx290_write_buffered_reg(imx290, IMX290_GAIN, 1, value);
450 dev_err(imx290->dev, "Unable to write gain\n");
456 static int imx290_stop_streaming(struct imx290 *imx290)
460 ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
466 return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
471 struct imx290 *imx290 = container_of(ctrl->handler,
472 struct imx290, ctrls);
476 if (!pm_runtime_get_if_in_use(imx290->dev))
481 ret = imx290_set_gain(imx290, ctrl->val);
485 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);
486 imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
488 imx290_write_reg(imx290, IMX290_PGCTRL,
493 imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
495 if (imx290->bpp == 10)
496 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
499 imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
501 imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
509 pm_runtime_put(imx290->dev);
534 const struct imx290 *imx290 = to_imx290(sd);
535 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
541 if (fse->index >= imx290_modes_num(imx290))
556 struct imx290 *imx290 = to_imx290(sd);
559 mutex_lock(&imx290->lock);
562 framefmt = v4l2_subdev_get_try_format(&imx290->sd, cfg,
565 framefmt = &imx290->current_format;
569 mutex_unlock(&imx290->lock);
574 static inline u8 imx290_get_link_freq_index(struct imx290 *imx290)
576 return imx290->current_mode->link_freq_index;
579 static s64 imx290_get_link_freq(struct imx290 *imx290)
581 u8 index = imx290_get_link_freq_index(imx290);
583 return *(imx290_link_freqs_ptr(imx290) + index);
586 static u64 imx290_calc_pixel_rate(struct imx290 *imx290)
588 s64 link_freq = imx290_get_link_freq(imx290);
589 u8 nlanes = imx290->nlanes;
594 do_div(pixel_rate, imx290->bpp);
602 struct imx290 *imx290 = to_imx290(sd);
607 mutex_lock(&imx290->lock);
609 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
610 imx290_modes_num(imx290), width, height,
629 format = &imx290->current_format;
630 imx290->current_mode = mode;
631 imx290->bpp = imx290_formats[i].bpp;
633 if (imx290->link_freq)
634 __v4l2_ctrl_s_ctrl(imx290->link_freq,
635 imx290_get_link_freq_index(imx290));
636 if (imx290->pixel_rate)
637 __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,
638 imx290_calc_pixel_rate(imx290));
643 mutex_unlock(&imx290->lock);
662 static int imx290_write_current_format(struct imx290 *imx290)
666 switch (imx290->current_format.code) {
668 ret = imx290_set_register_array(imx290, imx290_10bit_settings,
672 dev_err(imx290->dev, "Could not set format registers\n");
677 ret = imx290_set_register_array(imx290, imx290_12bit_settings,
681 dev_err(imx290->dev, "Could not set format registers\n");
686 dev_err(imx290->dev, "Unknown pixel format\n");
693 static int imx290_set_hmax(struct imx290 *imx290, u32 val)
697 ret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));
699 dev_err(imx290->dev, "Error setting HMAX register\n");
703 ret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));
705 dev_err(imx290->dev, "Error setting HMAX register\n");
713 static int imx290_start_streaming(struct imx290 *imx290)
718 ret = imx290_set_register_array(imx290, imx290_global_init_settings,
722 dev_err(imx290->dev, "Could not set init registers\n");
727 ret = imx290_write_current_format(imx290);
729 dev_err(imx290->dev, "Could not set frame format\n");
734 ret = imx290_set_register_array(imx290, imx290->current_mode->data,
735 imx290->current_mode->data_size);
737 dev_err(imx290->dev, "Could not set current mode\n");
740 ret = imx290_set_hmax(imx290, imx290->current_mode->hmax);
745 ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
747 dev_err(imx290->dev, "Could not sync v4l2 controls\n");
751 ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
758 return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
763 struct imx290 *imx290 = to_imx290(sd);
767 ret = pm_runtime_get_sync(imx290->dev);
769 pm_runtime_put_noidle(imx290->dev);
773 ret = imx290_start_streaming(imx290);
775 dev_err(imx290->dev, "Start stream failed\n");
776 pm_runtime_put(imx290->dev);
780 imx290_stop_streaming(imx290);
781 pm_runtime_put(imx290->dev);
789 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
794 imx290->supplies[i].supply = imx290_supply_name[i];
797 imx290->supplies);
800 static int imx290_set_data_lanes(struct imx290 *imx290)
804 switch (imx290->nlanes) {
818 dev_err(imx290->dev, "Lane configuration not supported\n");
823 ret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);
825 dev_err(imx290->dev, "Error setting Physical Lane number register\n");
829 ret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);
831 dev_err(imx290->dev, "Error setting CSI Lane mode register\n");
835 ret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);
837 dev_err(imx290->dev, "Error setting FR/FDG SEL register\n");
847 struct imx290 *imx290 = to_imx290(sd);
850 ret = clk_prepare_enable(imx290->xclk);
852 dev_err(imx290->dev, "Failed to enable clock\n");
856 ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
858 dev_err(imx290->dev, "Failed to enable regulators\n");
859 clk_disable_unprepare(imx290->xclk);
864 gpiod_set_value_cansleep(imx290->rst_gpio, 0);
868 imx290_set_data_lanes(imx290);
877 struct imx290 *imx290 = to_imx290(sd);
879 clk_disable_unprepare(imx290->xclk);
880 gpiod_set_value_cansleep(imx290->rst_gpio, 1);
881 regulator_bulk_disable(IMX290_NUM_SUPPLIES, imx290->supplies);
916 static s64 imx290_check_link_freqs(const struct imx290 *imx290,
920 const s64 *freqs = imx290_link_freqs_ptr(imx290);
921 int freqs_count = imx290_link_freqs_num(imx290);
941 struct imx290 *imx290;
946 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
947 if (!imx290)
950 imx290->dev = dev;
951 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
952 if (IS_ERR(imx290->regmap)) {
974 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
975 if (imx290->nlanes != 2 && imx290->nlanes != 4) {
976 dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes);
981 dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes);
990 fq = imx290_check_link_freqs(imx290, &ep);
998 imx290->xclk = devm_clk_get(dev, "xclk");
999 if (IS_ERR(imx290->xclk)) {
1001 ret = PTR_ERR(imx290->xclk);
1020 ret = clk_set_rate(imx290->xclk, xclk_freq);
1026 ret = imx290_get_regulators(dev, imx290);
1032 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
1034 if (IS_ERR(imx290->rst_gpio)) {
1036 ret = PTR_ERR(imx290->rst_gpio);
1040 mutex_init(&imx290->lock);
1043 * Initialize the frame format. In particular, imx290->current_mode
1044 * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call
1047 imx290_entity_init_cfg(&imx290->sd, NULL);
1049 v4l2_ctrl_handler_init(&imx290->ctrls, 4);
1051 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1054 imx290->link_freq =
1055 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
1057 imx290_link_freqs_num(imx290) - 1, 0,
1058 imx290_link_freqs_ptr(imx290));
1059 if (imx290->link_freq)
1060 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1062 imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
1065 imx290_calc_pixel_rate(imx290));
1067 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
1072 imx290->sd.ctrl_handler = &imx290->ctrls;
1074 if (imx290->ctrls.error) {
1076 imx290->ctrls.error);
1077 ret = imx290->ctrls.error;
1081 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
1082 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1083 imx290->sd.dev = &client->dev;
1084 imx290->sd.entity.ops = &imx290_subdev_entity_ops;
1085 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1087 imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
1088 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
1094 ret = v4l2_async_register_subdev(&imx290->sd);
1116 media_entity_cleanup(&imx290->sd.entity);
1118 v4l2_ctrl_handler_free(&imx290->ctrls);
1119 mutex_destroy(&imx290->lock);
1129 struct imx290 *imx290 = to_imx290(sd);
1135 mutex_destroy(&imx290->lock);
1137 pm_runtime_disable(imx290->dev);
1138 if (!pm_runtime_status_suspended(imx290->dev))
1139 imx290_power_off(imx290->dev);
1140 pm_runtime_set_suspended(imx290->dev);
1146 { .compatible = "sony,imx290" },
1155 .name = "imx290",