Lines Matching refs:x00
165 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
166 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
168 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
173 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
180 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
181 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
182 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
183 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
184 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
185 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
186 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
187 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
188 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
189 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
190 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
191 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
192 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
193 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
194 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
195 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
196 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
197 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
198 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
199 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
201 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
202 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
208 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
209 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
211 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
216 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
222 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
223 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
224 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
225 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
226 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
227 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
228 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
229 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
230 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
231 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
232 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
233 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
234 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
235 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
236 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
735 io_write_and_or(sd, 0x20, 0xcf, 0x00);
738 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
784 io_write_and_or(sd, 0x20, 0xcf, 0x00);
787 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
807 rep_write_and_or(sd, 0x77, 0xef, 0x00);
989 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1010 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1011 cp_write(sd, 0x26, 0x00);
1012 cp_write(sd, 0x27, 0x00);
1013 cp_write(sd, 0x28, 0x00);
1014 cp_write(sd, 0x29, 0x00);
1016 cp_write(sd, 0x90, 0x00);
1017 cp_write(sd, 0xa5, 0x00);
1018 cp_write(sd, 0xa6, 0x00);
1019 cp_write(sd, 0xa7, 0x00);
1020 cp_write(sd, 0xab, 0x00);
1021 cp_write(sd, 0xac, 0x00);
1074 io_write(sd, 0x00, 0x07); /* video std */
1102 io_write(sd, 0x00, 0x02); /* video std */
1217 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1241 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1637 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1685 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1727 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1729 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1750 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1756 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1802 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1807 afe_write(sd, 0x00, 0x00); /* power up ADC */
1808 afe_write(sd, 0xc8, 0x00); /* phase control */
1817 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1829 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1830 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1837 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1838 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1848 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1850 io_write(sd, 0x00, vid_std_select); /* video std */
1855 afe_write(sd, 0x00, 0x00); /* power up ADC */
1856 afe_write(sd, 0xc8, 0x00); /* phase control */
1875 cp_write(sd, 0x76, 0x00);
1884 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1887 hdmi_write(sd, 0x00, 0x02); /* select port A */
1889 hdmi_write(sd, 0x00, 0x03); /* select port B */
1890 io_write(sd, 0x00, vid_std_select); /* video std */
1892 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1898 hdmi_write(sd, 0xc0, 0x00);
1920 afe_write(sd, 0x00, 0xff); /* power down ADC */
1927 cp_write(sd, 0x76, 0x00);
1934 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
2267 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2269 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2271 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2589 { "AVI", 0x01, 0xe0, 0x00 },
2633 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2752 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2919 sdp_io_write(sd, 0x94, 0x00);
2920 sdp_io_write(sd, 0x95, 0x00);
2921 sdp_io_write(sd, 0x96, 0x00);
2923 sdp_io_write(sd, 0x98, 0x00);
2924 sdp_io_write(sd, 0x99, 0x00);
2925 sdp_io_write(sd, 0x9a, 0x00);
2926 sdp_io_write(sd, 0x9b, 0x00);
3039 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3046 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3073 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3103 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3104 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3113 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3118 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3127 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */