Lines Matching refs:sd
90 struct v4l2_subdev sd;
247 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
249 return container_of(sd, struct adv7842_state, sd);
254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
362 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
364 struct i2c_client *client = v4l2_get_subdevdata(sd);
369 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
371 struct i2c_client *client = v4l2_get_subdevdata(sd);
376 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
378 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
381 static inline int io_write_clr_set(struct v4l2_subdev *sd,
384 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
387 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
389 struct adv7842_state *state = to_state(sd);
394 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
396 struct adv7842_state *state = to_state(sd);
401 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
403 struct adv7842_state *state = to_state(sd);
408 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
410 struct adv7842_state *state = to_state(sd);
415 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
417 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
420 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
422 struct adv7842_state *state = to_state(sd);
427 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
429 struct adv7842_state *state = to_state(sd);
434 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
436 struct adv7842_state *state = to_state(sd);
441 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443 struct adv7842_state *state = to_state(sd);
448 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
450 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
453 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
455 struct adv7842_state *state = to_state(sd);
460 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
462 struct adv7842_state *state = to_state(sd);
467 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
469 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
472 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
474 struct adv7842_state *state = to_state(sd);
479 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
481 struct adv7842_state *state = to_state(sd);
486 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
488 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
491 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
493 struct adv7842_state *state = to_state(sd);
498 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
500 struct adv7842_state *state = to_state(sd);
505 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
507 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
510 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
512 struct adv7842_state *state = to_state(sd);
517 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
519 struct adv7842_state *state = to_state(sd);
524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
526 struct adv7842_state *state = to_state(sd);
531 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
533 struct adv7842_state *state = to_state(sd);
538 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
540 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
543 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
545 struct adv7842_state *state = to_state(sd);
550 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
552 struct adv7842_state *state = to_state(sd);
557 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
559 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
562 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
564 struct adv7842_state *state = to_state(sd);
569 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
571 struct adv7842_state *state = to_state(sd);
576 static void main_reset(struct v4l2_subdev *sd)
578 struct i2c_client *client = v4l2_get_subdevdata(sd);
580 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
647 static inline bool is_analog_input(struct v4l2_subdev *sd)
649 struct adv7842_state *state = to_state(sd);
655 static inline bool is_digital_input(struct v4l2_subdev *sd)
657 struct adv7842_state *state = to_state(sd);
685 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
687 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
693 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
695 u8 reg = io_read(sd, 0x6f);
710 struct v4l2_subdev *sd = &state->sd;
714 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
721 io_write_and_or(sd, 0x20, 0xcf, mask);
724 static int edid_write_vga_segment(struct v4l2_subdev *sd)
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
727 struct adv7842_state *state = to_state(sd);
732 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
735 io_write_and_or(sd, 0x20, 0xcf, 0x00);
738 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
741 rep_write_and_or(sd, 0x77, 0xef, 0x10);
752 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
755 if (rep_read(sd, 0x79) & 0x20)
770 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
772 struct i2c_client *client = v4l2_get_subdevdata(sd);
773 struct adv7842_state *state = to_state(sd);
780 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
784 io_write_and_or(sd, 0x20, 0xcf, 0x00);
787 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
807 rep_write_and_or(sd, 0x77, 0xef, 0x00);
816 rep_write(sd, 0x72, edid[spa_loc]);
817 rep_write(sd, 0x73, edid[spa_loc + 1]);
819 rep_write(sd, 0x74, edid[spa_loc]);
820 rep_write(sd, 0x75, edid[spa_loc + 1]);
822 rep_write(sd, 0x76, spa_loc & 0xff);
823 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
828 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
831 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
851 static void adv7842_inv_register(struct v4l2_subdev *sd)
853 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
854 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
855 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
856 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
857 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
858 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
859 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
860 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
861 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
862 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
863 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
864 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
867 static int adv7842_g_register(struct v4l2_subdev *sd,
873 reg->val = io_read(sd, reg->reg & 0xff);
876 reg->val = avlink_read(sd, reg->reg & 0xff);
879 reg->val = cec_read(sd, reg->reg & 0xff);
882 reg->val = infoframe_read(sd, reg->reg & 0xff);
885 reg->val = sdp_io_read(sd, reg->reg & 0xff);
888 reg->val = sdp_read(sd, reg->reg & 0xff);
891 reg->val = afe_read(sd, reg->reg & 0xff);
894 reg->val = rep_read(sd, reg->reg & 0xff);
897 reg->val = edid_read(sd, reg->reg & 0xff);
900 reg->val = hdmi_read(sd, reg->reg & 0xff);
903 reg->val = cp_read(sd, reg->reg & 0xff);
906 reg->val = vdp_read(sd, reg->reg & 0xff);
909 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
910 adv7842_inv_register(sd);
916 static int adv7842_s_register(struct v4l2_subdev *sd,
923 io_write(sd, reg->reg & 0xff, val);
926 avlink_write(sd, reg->reg & 0xff, val);
929 cec_write(sd, reg->reg & 0xff, val);
932 infoframe_write(sd, reg->reg & 0xff, val);
935 sdp_io_write(sd, reg->reg & 0xff, val);
938 sdp_write(sd, reg->reg & 0xff, val);
941 afe_write(sd, reg->reg & 0xff, val);
944 rep_write(sd, reg->reg & 0xff, val);
947 edid_write(sd, reg->reg & 0xff, val);
950 hdmi_write(sd, reg->reg & 0xff, val);
953 cp_write(sd, reg->reg & 0xff, val);
956 vdp_write(sd, reg->reg & 0xff, val);
959 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
960 adv7842_inv_register(sd);
967 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
969 struct adv7842_state *state = to_state(sd);
970 u16 cable_det = adv7842_read_cable_det(sd);
972 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
977 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
986 is_digital_input(sd) ? 250000 : 1000000, false))
989 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
991 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
998 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1001 struct adv7842_state *state = to_state(sd);
1004 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1007 io_write(sd, 0x16, 0x43);
1008 io_write(sd, 0x17, 0x5a);
1010 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1011 cp_write(sd, 0x26, 0x00);
1012 cp_write(sd, 0x27, 0x00);
1013 cp_write(sd, 0x28, 0x00);
1014 cp_write(sd, 0x29, 0x00);
1015 cp_write(sd, 0x8f, 0x40);
1016 cp_write(sd, 0x90, 0x00);
1017 cp_write(sd, 0xa5, 0x00);
1018 cp_write(sd, 0xa6, 0x00);
1019 cp_write(sd, 0xa7, 0x00);
1020 cp_write(sd, 0xab, 0x00);
1021 cp_write(sd, 0xac, 0x00);
1026 err = find_and_set_predefined_video_timings(sd,
1029 err = find_and_set_predefined_video_timings(sd,
1033 err = find_and_set_predefined_video_timings(sd,
1036 err = find_and_set_predefined_video_timings(sd,
1040 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1050 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1053 struct adv7842_state *state = to_state(sd);
1054 struct i2c_client *client = v4l2_get_subdevdata(sd);
1068 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1074 io_write(sd, 0x00, 0x07); /* video std */
1075 io_write(sd, 0x01, 0x02); /* prim mode */
1077 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1083 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1088 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1089 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1090 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1091 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1094 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1095 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1097 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1102 io_write(sd, 0x00, 0x02); /* video std */
1103 io_write(sd, 0x01, 0x06); /* prim mode */
1106 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1111 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1112 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1113 cp_write(sd, 0xab, (height >> 4) & 0xff);
1114 cp_write(sd, 0xac, (height & 0x0f) << 4);
1117 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1119 struct adv7842_state *state = to_state(sd);
1128 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1132 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1139 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1142 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1144 struct adv7842_state *state = to_state(sd);
1157 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1168 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1171 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1173 struct adv7842_state *state = to_state(sd);
1174 bool rgb_output = io_read(sd, 0x02) & 0x02;
1175 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1178 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1179 y = infoframe_read(sd, 0x01) >> 5;
1181 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1185 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1186 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1187 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1194 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1201 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1208 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1217 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1220 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1222 if (is_digital_input(sd) && rgb_output) {
1223 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1225 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1226 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1233 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1241 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1247 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1255 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1257 if (is_analog_input(sd) || hdmi_signal)
1262 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1264 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1265 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1273 struct v4l2_subdev *sd = to_sd(ctrl);
1274 struct adv7842_state *state = to_state(sd);
1283 cp_write(sd, 0x3c, ctrl->val);
1284 sdp_write(sd, 0x14, ctrl->val);
1288 cp_write(sd, 0x3a, ctrl->val);
1289 sdp_write(sd, 0x13, ctrl->val);
1293 cp_write(sd, 0x3b, ctrl->val);
1294 sdp_write(sd, 0x15, ctrl->val);
1298 cp_write(sd, 0x3d, ctrl->val);
1299 sdp_write(sd, 0x16, ctrl->val);
1304 afe_write(sd, 0xc8, ctrl->val);
1307 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1308 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1328 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1329 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1332 cp_write(sd, 0xc1, R);
1333 cp_write(sd, 0xc0, G);
1334 cp_write(sd, 0xc2, B);
1336 sdp_write(sd, 0xde, Y);
1337 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1342 set_rgb_quantization_range(sd);
1350 struct v4l2_subdev *sd = to_sd(ctrl);
1354 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1355 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1361 static inline bool no_power(struct v4l2_subdev *sd)
1363 return io_read(sd, 0x0c) & 0x24;
1366 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1368 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1371 static inline bool is_hdmi(struct v4l2_subdev *sd)
1373 return hdmi_read(sd, 0x05) & 0x80;
1376 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1378 struct adv7842_state *state = to_state(sd);
1382 if (io_read(sd, 0x0c) & 0x24)
1387 if (!(sdp_read(sd, 0x5A) & 0x01))
1390 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1395 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1396 !(cp_read(sd, 0xb1) & 0x80))
1400 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1403 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1415 static int stdi2dv_timings(struct v4l2_subdev *sd,
1419 struct adv7842_state *state = to_state(sd);
1428 adv7842_get_dv_timings_cap(sd),
1456 v4l2_dbg(2, debug, sd,
1463 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1467 adv7842_g_input_status(sd, &status);
1469 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1477 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1489 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1493 v4l2_dbg(2, debug, sd,
1502 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1509 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1512 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1518 *cap = *adv7842_get_dv_timings_cap(sd);
1524 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1527 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1528 is_digital_input(sd) ? 250000 : 1000000,
1533 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1536 struct adv7842_state *state = to_state(sd);
1540 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1549 if (read_stdi(sd, &stdi)) {
1551 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1559 if (is_digital_input(sd)) {
1564 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1565 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1566 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1567 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1568 if (is_hdmi(sd)) {
1570 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1573 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1574 hdmi_read(sd, 0x21);
1575 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1576 hdmi_read(sd, 0x23);
1577 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1578 hdmi_read(sd, 0x25);
1579 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1580 hdmi_read(sd, 0x2b)) / 2;
1581 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1582 hdmi_read(sd, 0x2f)) / 2;
1583 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1584 hdmi_read(sd, 0x33)) / 2;
1585 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1586 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1588 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1589 hdmi_read(sd, 0x0c);
1590 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1591 hdmi_read(sd, 0x2d)) / 2;
1592 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1593 hdmi_read(sd, 0x31)) / 2;
1594 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1595 hdmi_read(sd, 0x35)) / 2;
1601 adv7842_fill_optional_dv_timings_fields(sd, timings);
1615 if (!stdi2dv_timings(sd, &stdi, timings))
1618 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1619 if (!stdi2dv_timings(sd, &stdi, timings))
1622 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1623 if (stdi2dv_timings(sd, &stdi, timings)) {
1634 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1637 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1639 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1641 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1645 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1653 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1658 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1661 struct adv7842_state *state = to_state(sd);
1665 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1671 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1677 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1681 adv7842_fill_optional_dv_timings_fields(sd, timings);
1685 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1688 err = configure_predefined_video_timings(sd, timings);
1692 configure_custom_video_timings(sd, bt);
1695 set_rgb_quantization_range(sd);
1699 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1704 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1707 struct adv7842_state *state = to_state(sd);
1715 static void enable_input(struct v4l2_subdev *sd)
1717 struct adv7842_state *state = to_state(sd);
1719 set_rgb_quantization_range(sd);
1724 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1727 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1728 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1729 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1732 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1738 static void disable_input(struct v4l2_subdev *sd)
1740 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1742 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1743 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1746 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1750 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1756 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1759 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1760 sdp_io_write(sd, 0xe1, c->A1);
1761 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1762 sdp_io_write(sd, 0xe3, c->A2);
1763 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1764 sdp_io_write(sd, 0xe5, c->A3);
1767 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1768 sdp_io_write(sd, 0xe7, c->A4);
1771 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1772 sdp_io_write(sd, 0xe9, c->B1);
1773 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1774 sdp_io_write(sd, 0xeb, c->B2);
1775 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1776 sdp_io_write(sd, 0xed, c->B3);
1779 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1780 sdp_io_write(sd, 0xef, c->B4);
1783 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1784 sdp_io_write(sd, 0xf1, c->C1);
1785 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1786 sdp_io_write(sd, 0xf3, c->C2);
1787 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1788 sdp_io_write(sd, 0xf5, c->C3);
1791 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1792 sdp_io_write(sd, 0xf7, c->C4);
1795 static void select_input(struct v4l2_subdev *sd,
1798 struct adv7842_state *state = to_state(sd);
1802 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1803 io_write(sd, 0x01, 0); /* prim mode */
1805 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1807 afe_write(sd, 0x00, 0x00); /* power up ADC */
1808 afe_write(sd, 0xc8, 0x00); /* phase control */
1810 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1814 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1816 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1817 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1819 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1820 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1822 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1823 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1825 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1826 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1829 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1830 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1832 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1833 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1834 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1835 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1836 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1837 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1838 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1841 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1848 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1850 io_write(sd, 0x00, vid_std_select); /* video std */
1851 io_write(sd, 0x01, 0x02); /* prim mode */
1852 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1855 afe_write(sd, 0x00, 0x00); /* power up ADC */
1856 afe_write(sd, 0xc8, 0x00); /* phase control */
1859 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1862 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1868 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1869 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1872 cp_write(sd, 0x73, 0x10);
1873 cp_write(sd, 0x74, 0x04);
1874 cp_write(sd, 0x75, 0x01);
1875 cp_write(sd, 0x76, 0x00);
1877 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1878 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1879 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1884 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1887 hdmi_write(sd, 0x00, 0x02); /* select port A */
1889 hdmi_write(sd, 0x00, 0x03); /* select port B */
1890 io_write(sd, 0x00, vid_std_select); /* video std */
1891 io_write(sd, 0x01, 5); /* prim mode */
1892 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1898 hdmi_write(sd, 0xc0, 0x00);
1899 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1900 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1901 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1902 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1903 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1904 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1905 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1906 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1907 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1909 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1910 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1911 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1912 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1913 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1914 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1915 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1916 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1917 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1918 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1920 afe_write(sd, 0x00, 0xff); /* power down ADC */
1921 afe_write(sd, 0xc8, 0x40); /* phase control */
1924 cp_write(sd, 0x73, 0x10);
1925 cp_write(sd, 0x74, 0x04);
1926 cp_write(sd, 0x75, 0x01);
1927 cp_write(sd, 0x76, 0x00);
1932 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1933 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1934 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1937 cp_write(sd, 0xc3, 0x33); /* Component mode */
1940 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1944 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1950 static int adv7842_s_routing(struct v4l2_subdev *sd,
1953 struct adv7842_state *state = to_state(sd);
1955 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1988 disable_input(sd);
1989 select_input(sd, state->vid_std_select);
1990 enable_input(sd);
1992 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1997 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
2061 struct v4l2_subdev *sd = &state->sd;
2063 io_write_clr_set(sd, 0x02, 0x02,
2065 io_write(sd, 0x03, state->format->op_format_sel |
2067 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2068 io_write_clr_set(sd, 0x05, 0x01,
2070 set_rgb_quantization_range(sd);
2073 static int adv7842_get_format(struct v4l2_subdev *sd,
2077 struct adv7842_state *state = to_state(sd);
2084 if (!(sdp_read(sd, 0x5a) & 0x01))
2102 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2111 static int adv7842_set_format(struct v4l2_subdev *sd,
2115 struct adv7842_state *state = to_state(sd);
2122 return adv7842_get_format(sd, cfg, format);
2134 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2144 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2148 io_write(sd, 0x46, 0x9c);
2150 io_write(sd, 0x5a, 0x10);
2152 io_write(sd, 0x73, 0x03);
2154 io_write(sd, 0x78, 0x03);
2156 io_write(sd, 0xa0, 0x09);
2158 io_write(sd, 0x69, 0x08);
2160 io_write(sd, 0x46, 0x0);
2161 io_write(sd, 0x5a, 0x0);
2162 io_write(sd, 0x73, 0x0);
2163 io_write(sd, 0x78, 0x0);
2164 io_write(sd, 0xa0, 0x0);
2165 io_write(sd, 0x69, 0x0);
2170 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2172 struct adv7842_state *state = to_state(sd);
2174 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2175 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2180 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2191 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2197 nack_cnt = cec_read(sd, 0x14) & 0xf;
2200 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2208 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2214 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2219 cec_irq = io_read(sd, 0x93) & 0x0f;
2223 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2224 adv7842_cec_tx_raw_status(sd, cec_irq);
2226 struct adv7842_state *state = to_state(sd);
2229 msg.len = cec_read(sd, 0x25) & 0x1f;
2237 msg.msg[i] = cec_read(sd, i + 0x15);
2238 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2243 io_write(sd, 0x94, cec_irq);
2252 struct v4l2_subdev *sd = &state->sd;
2255 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2256 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2257 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2263 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2264 cec_write(sd, 0x26, 0x01); /* enable rx */
2267 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2269 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2271 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2281 struct v4l2_subdev *sd = &state->sd;
2288 cec_write_clr_set(sd, 0x27, 0x70, 0);
2312 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2314 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2318 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2320 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2324 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2326 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2336 struct v4l2_subdev *sd = &state->sd;
2345 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2348 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2354 cec_write(sd, i, msg->msg[i]);
2357 cec_write(sd, 0x10, len);
2359 cec_write(sd, 0x11, 0x01);
2370 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2372 struct adv7842_state *state = to_state(sd);
2376 adv7842_irq_enable(sd, false);
2379 irq_status[0] = io_read(sd, 0x43);
2380 irq_status[1] = io_read(sd, 0x57);
2381 irq_status[2] = io_read(sd, 0x70);
2382 irq_status[3] = io_read(sd, 0x75);
2383 irq_status[4] = io_read(sd, 0x9d);
2384 irq_status[5] = io_read(sd, 0x66);
2388 io_write(sd, 0x44, irq_status[0]);
2390 io_write(sd, 0x58, irq_status[1]);
2392 io_write(sd, 0x71, irq_status[2]);
2394 io_write(sd, 0x76, irq_status[3]);
2396 io_write(sd, 0x9e, irq_status[4]);
2398 io_write(sd, 0x67, irq_status[5]);
2400 adv7842_irq_enable(sd, true);
2402 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2416 if (is_digital_input(sd))
2423 v4l2_dbg(1, debug, sd,
2427 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2434 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2435 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2436 set_rgb_quantization_range(sd);
2443 adv7842_cec_isr(sd, handled);
2448 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2449 adv7842_s_detect_tx_5v_ctrl(sd);
2456 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2458 struct adv7842_state *state = to_state(sd);
2496 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2498 struct adv7842_state *state = to_state(sd);
2521 err = edid_write_vga_segment(sd);
2530 adv7842_s_detect_tx_5v_ctrl(sd);
2533 err = edid_write_hdmi_segment(sd, e->pad);
2539 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2550 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)
2556 struct i2c_client *client = v4l2_get_subdevdata(sd);
2559 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2560 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2565 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2570 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2575 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2578 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2585 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2595 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2596 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2601 log_infoframe(sd, &cri[i]);
2626 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2629 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2631 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2632 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2633 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2635 v4l2_info(sd, "SDP: free run: %s\n",
2636 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2637 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2654 v4l2_info(sd, "SDP: standard %s\n",
2655 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2656 v4l2_info(sd, "SDP: %s\n",
2657 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2658 v4l2_info(sd, "SDP: %s\n",
2659 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2660 v4l2_info(sd, "SDP: deinterlacer %s\n",
2661 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2662 v4l2_info(sd, "SDP: csc %s mode\n",
2663 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2668 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2671 struct adv7842_state *state = to_state(sd);
2673 u8 reg_io_0x02 = io_read(sd, 0x02);
2674 u8 reg_io_0x21 = io_read(sd, 0x21);
2675 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2676 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2677 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2678 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2679 bool audio_mute = io_read(sd, 0x65) & 0x40;
2707 v4l2_info(sd, "-----Chip status-----\n");
2708 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2709 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2711 v4l2_info(sd, "EDID A %s, B %s\n",
2716 v4l2_info(sd, "HPD A %s, B %s\n",
2719 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2728 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2733 v4l2_info(sd, "-----Signal status-----\n");
2735 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2736 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2737 v4l2_info(sd, "TMDS signal detected: %s\n",
2738 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2739 v4l2_info(sd, "TMDS signal locked: %s\n",
2740 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2742 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2743 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2744 v4l2_info(sd, "TMDS signal detected: %s\n",
2745 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2746 v4l2_info(sd, "TMDS signal locked: %s\n",
2747 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2749 v4l2_info(sd, "CP free run: %s\n",
2750 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2751 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2752 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2753 (io_read(sd, 0x01) & 0x70) >> 4);
2755 v4l2_info(sd, "-----Video Timings-----\n");
2756 if (no_cp_signal(sd)) {
2757 v4l2_info(sd, "STDI: not locked\n");
2759 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2760 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2761 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2762 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2763 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2764 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2765 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2766 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2767 v4l2_info(sd,
2770 (cp_read(sd, 0xb1) & 0x40) ?
2774 if (adv7842_query_dv_timings(sd, &timings))
2775 v4l2_info(sd, "No video detected\n");
2777 v4l2_print_dv_timings(sd->name, "Detected format: ",
2779 v4l2_print_dv_timings(sd->name, "Configured format: ",
2782 if (no_cp_signal(sd))
2785 v4l2_info(sd, "-----Color space-----\n");
2786 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2788 v4l2_info(sd, "Input color space: %s\n",
2790 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2795 v4l2_info(sd, "Color space conversion: %s\n",
2796 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2798 if (!is_digital_input(sd))
2801 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2802 v4l2_info(sd, "HDCP encrypted content: %s\n",
2803 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2804 v4l2_info(sd, "HDCP keys read: %s%s\n",
2805 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2806 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2807 if (!is_hdmi(sd))
2810 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2815 v4l2_info(sd, "Audio format: %s\n",
2816 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2818 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2819 (hdmi_read(sd, 0x5c) << 8) +
2820 (hdmi_read(sd, 0x5d) & 0xf0));
2821 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2822 (hdmi_read(sd, 0x5e) << 8) +
2823 hdmi_read(sd, 0x5f));
2824 v4l2_info(sd, "AV Mute: %s\n",
2825 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2826 v4l2_info(sd, "Deep color mode: %s\n",
2827 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2829 adv7842_log_infoframes(sd);
2834 static int adv7842_log_status(struct v4l2_subdev *sd)
2836 struct adv7842_state *state = to_state(sd);
2839 return adv7842_sdp_log_status(sd);
2840 return adv7842_cp_log_status(sd);
2843 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2845 struct adv7842_state *state = to_state(sd);
2847 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2852 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2854 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2858 switch (sdp_read(sd, 0x52) & 0x0f) {
2898 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2901 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2902 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2903 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2904 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2905 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2906 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2907 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2908 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2909 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2910 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2911 sdp_io_write(sd, 0xaa, s->vs_end_o);
2912 sdp_io_write(sd, 0xab, s->vs_end_e);
2913 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2914 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2915 sdp_io_write(sd, 0xae, s->de_v_end_o);
2916 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2919 sdp_io_write(sd, 0x94, 0x00);
2920 sdp_io_write(sd, 0x95, 0x00);
2921 sdp_io_write(sd, 0x96, 0x00);
2922 sdp_io_write(sd, 0x97, 0x20);
2923 sdp_io_write(sd, 0x98, 0x00);
2924 sdp_io_write(sd, 0x99, 0x00);
2925 sdp_io_write(sd, 0x9a, 0x00);
2926 sdp_io_write(sd, 0x9b, 0x00);
2927 sdp_io_write(sd, 0xa8, 0x04);
2928 sdp_io_write(sd, 0xa9, 0x04);
2929 sdp_io_write(sd, 0xaa, 0x04);
2930 sdp_io_write(sd, 0xab, 0x04);
2931 sdp_io_write(sd, 0xac, 0x04);
2932 sdp_io_write(sd, 0xad, 0x04);
2933 sdp_io_write(sd, 0xae, 0x04);
2934 sdp_io_write(sd, 0xaf, 0x04);
2938 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2940 struct adv7842_state *state = to_state(sd);
2943 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2949 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2951 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2953 adv7842_s_sdp_io(sd, NULL);
2962 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2964 struct adv7842_state *state = to_state(sd);
2966 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2977 static int adv7842_core_init(struct v4l2_subdev *sd)
2979 struct adv7842_state *state = to_state(sd);
2981 hdmi_write(sd, 0x48,
2985 disable_input(sd);
2991 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2994 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2995 io_write(sd, 0x15, 0x80); /* Power up pads */
2998 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
2999 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3005 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3008 io_write_and_or(sd, 0x14, 0xc0,
3014 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3018 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3024 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3025 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3026 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3027 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3029 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3030 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3032 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3036 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3039 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3040 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3041 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3042 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3043 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3045 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3046 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3047 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3049 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3050 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3051 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3052 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3059 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3062 select_input(sd, pdata->vid_std_select);
3064 enable_input(sd);
3068 hdmi_write(sd, 0x69, 0x5c);
3071 hdmi_write(sd, 0x69, 0xa3);
3073 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3077 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3078 io_write(sd, 0x33, 0x40);
3081 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3083 adv7842_irq_enable(sd, true);
3085 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3090 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3103 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3104 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3105 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
3106 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
3107 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
3108 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
3109 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
3110 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3111 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3112 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3113 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3114 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3118 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3119 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3120 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3121 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3122 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3123 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3124 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3125 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3126 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3127 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3128 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3132 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3133 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3138 u8 result = sdp_io_read(sd, 0xdb);
3149 v4l2_dbg(1, debug, sd,
3158 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3161 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3162 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3163 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3164 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3165 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3167 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3168 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3169 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3170 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3172 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3173 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3176 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3178 struct i2c_client *client = v4l2_get_subdevdata(sd);
3179 struct adv7842_state *state = to_state(sd);
3188 v4l2_info(sd, "no sdram or no ddr sdram\n");
3192 main_reset(sd);
3194 adv7842_rewrite_i2c_addresses(sd, pdata);
3197 ret = adv7842_ddr_ram_test(sd);
3199 main_reset(sd);
3201 adv7842_rewrite_i2c_addresses(sd, pdata);
3204 adv7842_core_init(sd);
3206 disable_input(sd);
3208 select_input(sd, state->vid_std_select);
3210 enable_input(sd);
3212 edid_write_vga_segment(sd);
3213 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3214 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3220 adv7842_s_dv_timings(sd, &timings);
3225 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3229 return adv7842_command_ram_test(sd);
3234 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3240 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3242 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3248 static int adv7842_registered(struct v4l2_subdev *sd)
3250 struct adv7842_state *state = to_state(sd);
3251 struct i2c_client *client = v4l2_get_subdevdata(sd);
3260 static void adv7842_unregistered(struct v4l2_subdev *sd)
3262 struct adv7842_state *state = to_state(sd);
3351 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3353 struct adv7842_state *state = to_state(sd);
3379 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3382 struct i2c_client *client = v4l2_get_subdevdata(sd);
3385 io_write(sd, io_reg, addr << 1);
3388 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3392 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
3394 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",
3402 static int adv7842_register_clients(struct v4l2_subdev *sd)
3404 struct adv7842_state *state = to_state(sd);
3407 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3408 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3409 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3410 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3411 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3412 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3413 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3414 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3415 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3416 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3417 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3444 struct v4l2_subdev *sd;
3469 sd = &state->sd;
3470 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3471 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3472 sd->internal_ops = &adv7842_int_ops;
3482 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3487 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3493 main_reset(sd);
3527 sd->ctrl_handler = hdl;
3532 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3537 if (adv7842_register_clients(sd) < 0) {
3539 v4l2_err(sd, "failed to create all i2c clients\n");
3547 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3549 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
3553 err = adv7842_core_init(sd);
3566 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3571 media_entity_cleanup(&sd->entity);
3575 adv7842_unregister_clients(sd);
3585 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3586 struct adv7842_state *state = to_state(sd);
3588 adv7842_irq_enable(sd, false);
3590 v4l2_device_unregister_subdev(sd);
3591 media_entity_cleanup(&sd->entity);
3592 adv7842_unregister_clients(sd);
3593 v4l2_ctrl_handler_free(sd->ctrl_handler);