Lines Matching refs:sd
126 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
127 void (*setup_irqs)(struct v4l2_subdev *sd);
128 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
129 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
167 struct v4l2_subdev sd;
320 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
322 return container_of(sd, struct adv76xx_state, sd);
374 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
376 struct adv76xx_state *state = to_state(sd);
381 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383 struct adv76xx_state *state = to_state(sd);
388 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
391 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
394 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
396 struct adv76xx_state *state = to_state(sd);
401 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
403 struct adv76xx_state *state = to_state(sd);
408 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
410 struct adv76xx_state *state = to_state(sd);
415 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
417 struct adv76xx_state *state = to_state(sd);
422 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
425 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
428 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
430 struct adv76xx_state *state = to_state(sd);
435 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
437 struct adv76xx_state *state = to_state(sd);
442 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
444 struct adv76xx_state *state = to_state(sd);
449 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
451 struct adv76xx_state *state = to_state(sd);
456 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
458 struct adv76xx_state *state = to_state(sd);
463 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
465 struct adv76xx_state *state = to_state(sd);
470 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
472 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
475 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
477 struct adv76xx_state *state = to_state(sd);
482 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
484 struct adv76xx_state *state = to_state(sd);
489 static inline int edid_write_block(struct v4l2_subdev *sd,
492 struct adv76xx_state *state = to_state(sd);
497 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
520 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
528 struct v4l2_subdev *sd = &state->sd;
530 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
535 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
537 struct adv76xx_state *state = to_state(sd);
542 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
544 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
547 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
549 struct adv76xx_state *state = to_state(sd);
554 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
556 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
559 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
561 struct adv76xx_state *state = to_state(sd);
566 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
568 struct adv76xx_state *state = to_state(sd);
573 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
575 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
580 struct adv76xx_state *state = to_state(sd);
585 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
587 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
592 struct adv76xx_state *state = to_state(sd);
597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
599 struct adv76xx_state *state = to_state(sd);
608 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
610 struct adv76xx_state *state = to_state(sd);
625 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
627 struct adv76xx_state *state = to_state(sd);
638 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
644 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
753 static inline bool is_analog_input(struct v4l2_subdev *sd)
755 struct adv76xx_state *state = to_state(sd);
761 static inline bool is_digital_input(struct v4l2_subdev *sd)
763 struct adv76xx_state *state = to_state(sd);
798 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
801 struct adv76xx_state *state = to_state(sd);
824 static void adv76xx_inv_register(struct v4l2_subdev *sd)
826 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
827 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
828 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
829 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
830 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
831 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
832 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
833 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
834 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
835 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
836 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
837 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
838 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
841 static int adv76xx_g_register(struct v4l2_subdev *sd,
846 ret = adv76xx_read_reg(sd, reg->reg);
848 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
849 adv76xx_inv_register(sd);
859 static int adv76xx_s_register(struct v4l2_subdev *sd,
864 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
866 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
867 adv76xx_inv_register(sd);
875 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
877 u8 value = io_read(sd, 0x6f);
885 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
887 u8 value = io_read(sd, 0x6f);
892 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
897 u8 value = io_read(sd, 0x6f);
902 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
904 struct adv76xx_state *state = to_state(sd);
906 u16 cable_det = info->read_cable_det(sd);
911 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
920 is_digital_input(sd) ? 250000 : 1000000, false))
922 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
923 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
931 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
934 struct adv76xx_state *state = to_state(sd);
937 v4l2_dbg(1, debug, sd, "%s", __func__);
941 io_write(sd, 0x16, 0x43);
942 io_write(sd, 0x17, 0x5a);
945 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
946 cp_write(sd, 0x8f, 0x00);
947 cp_write(sd, 0x90, 0x00);
948 cp_write(sd, 0xa2, 0x00);
949 cp_write(sd, 0xa3, 0x00);
950 cp_write(sd, 0xa4, 0x00);
951 cp_write(sd, 0xa5, 0x00);
952 cp_write(sd, 0xa6, 0x00);
953 cp_write(sd, 0xa7, 0x00);
954 cp_write(sd, 0xab, 0x00);
955 cp_write(sd, 0xac, 0x00);
957 if (is_analog_input(sd)) {
958 err = find_and_set_predefined_video_timings(sd,
961 err = find_and_set_predefined_video_timings(sd,
963 } else if (is_digital_input(sd)) {
964 err = find_and_set_predefined_video_timings(sd,
967 err = find_and_set_predefined_video_timings(sd,
970 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
979 static void configure_custom_video_timings(struct v4l2_subdev *sd,
982 struct adv76xx_state *state = to_state(sd);
996 v4l2_dbg(2, debug, sd, "%s\n", __func__);
998 if (is_analog_input(sd)) {
1000 io_write(sd, 0x00, 0x07); /* video std */
1001 io_write(sd, 0x01, 0x02); /* prim mode */
1003 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1010 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1013 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1014 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1016 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1019 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1020 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1022 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1023 } else if (is_digital_input(sd)) {
1026 io_write(sd, 0x00, 0x02); /* video std */
1027 io_write(sd, 0x01, 0x06); /* prim mode */
1029 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1033 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1034 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1035 cp_write(sd, 0xab, (height >> 4) & 0xff);
1036 cp_write(sd, 0xac, (height & 0x0f) << 4);
1039 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1041 struct adv76xx_state *state = to_state(sd);
1050 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1054 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1062 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1065 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1067 struct adv76xx_state *state = to_state(sd);
1080 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1092 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1095 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1097 struct adv76xx_state *state = to_state(sd);
1098 bool rgb_output = io_read(sd, 0x02) & 0x02;
1099 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1102 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1103 y = infoframe_read(sd, 0x01) >> 5;
1105 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1109 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1110 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1111 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1118 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1125 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1132 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1141 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1144 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1146 if (is_digital_input(sd) && rgb_output) {
1147 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1149 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1150 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1157 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1165 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1171 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1179 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1181 if (is_analog_input(sd) || hdmi_signal)
1186 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1188 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1189 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1197 struct v4l2_subdev *sd =
1198 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1200 struct adv76xx_state *state = to_state(sd);
1204 cp_write(sd, 0x3c, ctrl->val);
1207 cp_write(sd, 0x3a, ctrl->val);
1210 cp_write(sd, 0x3b, ctrl->val);
1213 cp_write(sd, 0x3d, ctrl->val);
1217 set_rgb_quantization_range(sd);
1226 afe_write(sd, 0xc8, ctrl->val);
1231 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1234 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1235 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1236 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1244 struct v4l2_subdev *sd =
1245 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1249 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1250 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1258 static inline bool no_power(struct v4l2_subdev *sd)
1261 return io_read(sd, 0x0c) & 0x24;
1264 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1266 struct adv76xx_state *state = to_state(sd);
1268 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1271 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1273 struct adv76xx_state *state = to_state(sd);
1276 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1279 static inline bool is_hdmi(struct v4l2_subdev *sd)
1281 return hdmi_read(sd, 0x05) & 0x80;
1284 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1286 struct adv76xx_state *state = to_state(sd);
1296 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1299 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1302 return !(cp_read(sd, 0xb1) & 0x80);
1305 static inline bool no_signal(struct v4l2_subdev *sd)
1309 ret = no_power(sd);
1311 ret |= no_lock_stdi(sd);
1312 ret |= no_lock_sspd(sd);
1314 if (is_digital_input(sd)) {
1315 ret |= no_lock_tmds(sd);
1316 ret |= no_signal_tmds(sd);
1322 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1324 struct adv76xx_state *state = to_state(sd);
1331 return io_read(sd, 0x12) & 0x01;
1334 static inline bool in_free_run(struct v4l2_subdev *sd)
1336 return cp_read(sd, 0xff) & 0x10;
1339 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1342 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1343 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1344 if (!in_free_run(sd) && no_lock_cp(sd))
1345 *status |= is_digital_input(sd) ?
1348 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1361 static int stdi2dv_timings(struct v4l2_subdev *sd,
1365 struct adv76xx_state *state = to_state(sd);
1374 adv76xx_get_dv_timings_cap(sd, -1),
1402 v4l2_dbg(2, debug, sd,
1410 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1412 struct adv76xx_state *state = to_state(sd);
1416 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1417 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1422 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1423 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1424 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1425 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1429 polarity = cp_read(sd, 0xb5);
1440 polarity = hdmi_read(sd, 0x05);
1445 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1446 v4l2_dbg(2, debug, sd,
1452 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1457 v4l2_dbg(2, debug, sd,
1466 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1469 struct adv76xx_state *state = to_state(sd);
1475 adv76xx_get_dv_timings_cap(sd, timings->pad),
1479 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1482 struct adv76xx_state *state = to_state(sd);
1488 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1496 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1499 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1500 is_digital_input(sd) ? 250000 : 1000000,
1504 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1508 a = hdmi_read(sd, 0x06);
1509 b = hdmi_read(sd, 0x3b);
1516 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1520 a = hdmi_read(sd, 0x51);
1521 b = hdmi_read(sd, 0x52);
1528 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1530 struct adv76xx_state *state = to_state(sd);
1534 freq = info->read_hdmi_pixelclock(sd);
1535 if (is_hdmi(sd)) {
1537 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1538 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1546 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1549 struct adv76xx_state *state = to_state(sd);
1559 if (no_signal(sd)) {
1561 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1566 if (read_stdi(sd, &stdi)) {
1567 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1573 if (is_digital_input(sd)) {
1574 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1578 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1579 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1581 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1582 vic = infoframe_read(sd, 0x04);
1592 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
1593 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1594 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1595 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1596 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1598 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1599 bt->vbackporch = hdmi_read16(sd, 0x32,
1601 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1602 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1604 bt->height += hdmi_read16(sd, 0x0b,
1606 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1608 bt->il_vsync = hdmi_read16(sd, 0x30,
1610 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1613 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1619 if (!stdi2dv_timings(sd, &stdi, timings))
1622 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1623 if (!stdi2dv_timings(sd, &stdi, timings))
1626 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1627 if (stdi2dv_timings(sd, &stdi, timings)) {
1638 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1641 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1643 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1645 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1649 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1656 if (no_signal(sd)) {
1657 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1662 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1663 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1664 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1670 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1676 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1679 struct adv76xx_state *state = to_state(sd);
1687 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1693 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1697 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1701 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1704 err = configure_predefined_video_timings(sd, timings);
1708 configure_custom_video_timings(sd, bt);
1711 set_rgb_quantization_range(sd);
1714 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1719 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1722 struct adv76xx_state *state = to_state(sd);
1728 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1730 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1733 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1735 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1738 static void enable_input(struct v4l2_subdev *sd)
1740 struct adv76xx_state *state = to_state(sd);
1742 if (is_analog_input(sd)) {
1743 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1744 } else if (is_digital_input(sd)) {
1745 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1746 state->info->set_termination(sd, true);
1747 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1748 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1750 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1755 static void disable_input(struct v4l2_subdev *sd)
1757 struct adv76xx_state *state = to_state(sd);
1759 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1761 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1762 state->info->set_termination(sd, false);
1765 static void select_input(struct v4l2_subdev *sd)
1767 struct adv76xx_state *state = to_state(sd);
1770 if (is_analog_input(sd)) {
1771 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1773 afe_write(sd, 0x00, 0x08); /* power up ADC */
1774 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1775 afe_write(sd, 0xc8, 0x00); /* phase control */
1776 } else if (is_digital_input(sd)) {
1777 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1779 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1782 afe_write(sd, 0x00, 0xff); /* power down ADC */
1783 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1784 afe_write(sd, 0xc8, 0x40); /* phase control */
1787 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1788 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1789 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1791 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1796 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1799 struct adv76xx_state *state = to_state(sd);
1801 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1812 disable_input(sd);
1813 select_input(sd);
1814 enable_input(sd);
1816 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1821 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1825 struct adv76xx_state *state = to_state(sd);
1889 struct v4l2_subdev *sd = &state->sd;
1891 io_write_clr_set(sd, 0x02, 0x02,
1893 io_write(sd, 0x03, state->format->op_format_sel |
1895 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1896 io_write_clr_set(sd, 0x05, 0x01,
1898 set_rgb_quantization_range(sd);
1901 static int adv76xx_get_format(struct v4l2_subdev *sd,
1905 struct adv76xx_state *state = to_state(sd);
1915 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1924 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1928 struct adv76xx_state *state = to_state(sd);
1944 static int adv76xx_set_format(struct v4l2_subdev *sd,
1948 struct adv76xx_state *state = to_state(sd);
1964 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1975 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1977 struct adv76xx_state *state = to_state(sd);
1979 if ((cec_read(sd, 0x11) & 0x01) == 0) {
1980 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1985 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
1996 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2002 nack_cnt = cec_read(sd, 0x14) & 0xf;
2005 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2013 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2019 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2021 struct adv76xx_state *state = to_state(sd);
2026 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2030 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2031 adv76xx_cec_tx_raw_status(sd, cec_irq);
2035 msg.len = cec_read(sd, 0x25) & 0x1f;
2043 msg.msg[i] = cec_read(sd, i + 0x15);
2044 cec_write(sd, info->cec_rx_enable,
2058 io_write(sd, info->cec_irq_status + 1, cec_irq);
2068 struct v4l2_subdev *sd = &state->sd;
2071 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2072 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2073 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2079 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2080 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2083 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2085 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2087 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2091 adv76xx_s_detect_tx_5v_ctrl(sd);
2098 struct v4l2_subdev *sd = &state->sd;
2105 cec_write_clr_set(sd, 0x27, 0x70, 0);
2129 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2131 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2135 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2137 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2141 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2143 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2153 struct v4l2_subdev *sd = &state->sd;
2162 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2165 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2171 cec_write(sd, i, msg->msg[i]);
2174 cec_write(sd, 0x10, len);
2176 cec_write(sd, 0x11, 0x01);
2187 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2189 struct adv76xx_state *state = to_state(sd);
2191 const u8 irq_reg_0x43 = io_read(sd, 0x43);
2192 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2193 const u8 irq_reg_0x70 = io_read(sd, 0x70);
2199 io_write(sd, 0x44, irq_reg_0x43);
2201 io_write(sd, 0x71, irq_reg_0x70);
2203 io_write(sd, 0x6c, irq_reg_0x6b);
2205 v4l2_dbg(2, debug, sd, "%s: ", __func__);
2209 fmt_change_digital = is_digital_input(sd)
2214 v4l2_dbg(1, debug, sd,
2218 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2225 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2226 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2227 set_rgb_quantization_range(sd);
2234 adv76xx_cec_isr(sd, handled);
2240 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2241 adv76xx_s_detect_tx_5v_ctrl(sd);
2253 adv76xx_isr(&state->sd, 0, &handled);
2258 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2260 struct adv76xx_state *state = to_state(sd);
2296 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2298 struct adv76xx_state *state = to_state(sd);
2315 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2326 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2339 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2345 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2360 rep_write(sd, 0x70, edid->edid[spa_loc]);
2361 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2364 rep_write(sd, 0x72, edid->edid[spa_loc]);
2365 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2368 rep_write(sd, 0x74, edid->edid[spa_loc]);
2369 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2376 rep_write(sd, 0x76, spa_loc & 0xff);
2377 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2380 rep_write(sd, 0x70, spa_loc & 0xff);
2381 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2393 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2395 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2401 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2404 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2409 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2428 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2435 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2436 v4l2_info(sd, "%s infoframe not received\n",
2442 buffer[i] = infoframe_read(sd,
2448 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2454 buffer[i + 3] = infoframe_read(sd,
2458 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2465 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2469 if (!is_hdmi(sd)) {
2470 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2476 struct i2c_client *client = v4l2_get_subdevdata(sd);
2478 if (adv76xx_read_infoframe(sd, i, &frame))
2484 static int adv76xx_log_status(struct v4l2_subdev *sd)
2486 struct adv76xx_state *state = to_state(sd);
2490 u8 reg_io_0x02 = io_read(sd, 0x02);
2528 v4l2_info(sd, "-----Chip status-----\n");
2529 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2530 edid_enabled = rep_read(sd, info->edid_status_reg);
2531 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2536 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2545 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2550 v4l2_info(sd, "-----Signal status-----\n");
2551 cable_det = info->read_cable_det(sd);
2552 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2557 v4l2_info(sd, "TMDS signal detected: %s\n",
2558 no_signal_tmds(sd) ? "false" : "true");
2559 v4l2_info(sd, "TMDS signal locked: %s\n",
2560 no_lock_tmds(sd) ? "false" : "true");
2561 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2562 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2563 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2564 v4l2_info(sd, "CP free run: %s\n",
2565 (in_free_run(sd)) ? "on" : "off");
2566 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2567 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2568 (io_read(sd, 0x01) & 0x70) >> 4);
2570 v4l2_info(sd, "-----Video Timings-----\n");
2571 if (read_stdi(sd, &stdi))
2572 v4l2_info(sd, "STDI: not locked\n");
2574 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2578 if (adv76xx_query_dv_timings(sd, &timings))
2579 v4l2_info(sd, "No video detected\n");
2581 v4l2_print_dv_timings(sd->name, "Detected format: ",
2583 v4l2_print_dv_timings(sd->name, "Configured format: ",
2586 if (no_signal(sd))
2589 v4l2_info(sd, "-----Color space-----\n");
2590 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2592 v4l2_info(sd, "Input color space: %s\n",
2594 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2599 v4l2_info(sd, "Color space conversion: %s\n",
2600 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2602 if (!is_digital_input(sd))
2605 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2606 v4l2_info(sd, "Digital video port selected: %c\n",
2607 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2608 v4l2_info(sd, "HDCP encrypted content: %s\n",
2609 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2610 v4l2_info(sd, "HDCP keys read: %s%s\n",
2611 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2612 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2613 if (is_hdmi(sd)) {
2614 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2615 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2616 bool audio_mute = io_read(sd, 0x65) & 0x40;
2618 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2623 v4l2_info(sd, "Audio format: %s\n",
2624 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2626 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2627 (hdmi_read(sd, 0x5c) << 8) +
2628 (hdmi_read(sd, 0x5d) & 0xf0));
2629 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2630 (hdmi_read(sd, 0x5e) << 8) +
2631 hdmi_read(sd, 0x5f));
2632 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2634 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2635 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2637 adv76xx_log_infoframes(sd);
2643 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2649 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2651 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2657 static int adv76xx_registered(struct v4l2_subdev *sd)
2659 struct adv76xx_state *state = to_state(sd);
2660 struct i2c_client *client = v4l2_get_subdevdata(sd);
2669 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2671 struct adv76xx_state *state = to_state(sd);
2782 static int adv76xx_core_init(struct v4l2_subdev *sd)
2784 struct adv76xx_state *state = to_state(sd);
2788 hdmi_write(sd, 0x48,
2792 disable_input(sd);
2797 select_input(sd);
2798 enable_input(sd);
2802 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2803 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2804 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2807 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2808 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2813 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2816 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2820 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2824 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2825 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2826 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2828 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2830 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2834 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2835 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2836 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2839 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2842 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2843 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2847 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2848 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2849 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2850 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2851 info->setup_irqs(sd);
2853 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2856 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2858 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2861 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2863 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2866 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2868 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2879 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2882 struct i2c_client *client = v4l2_get_subdevdata(sd);
2883 struct adv76xx_state *state = to_state(sd);
2897 io_write(sd, io_reg, new_client->addr << 1);
3357 struct v4l2_subdev *sd;
3420 sd = &state->sd;
3421 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3422 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3425 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3426 sd->internal_ops = &adv76xx_int_ops;
3432 v4l2_err(sd, "Error configuring IO regmap region\n");
3445 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3449 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3460 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3468 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3474 v4l2_err(sd, "not an adv761x on address 0x%x\n",
3516 sd->ctrl_handler = hdl;
3521 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3532 dummy_client = adv76xx_dummy_client(sd, i);
3535 v4l2_err(sd, "failed to create i2c client %u\n", i);
3550 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3552 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3562 err = adv76xx_core_init(sd);
3585 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3588 err = v4l2_async_register_subdev(sd);
3595 media_entity_cleanup(&sd->entity);
3609 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3610 struct adv76xx_state *state = to_state(sd);
3613 io_write(sd, 0x40, 0);
3614 io_write(sd, 0x41, 0);
3615 io_write(sd, 0x46, 0);
3616 io_write(sd, 0x6e, 0);
3617 io_write(sd, 0x73, 0);
3620 v4l2_async_unregister_subdev(sd);
3621 media_entity_cleanup(&sd->entity);
3622 adv76xx_unregister_clients(to_state(sd));
3623 v4l2_ctrl_handler_free(sd->ctrl_handler);