Lines Matching defs:adv7180_write
235 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
497 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
548 ret = adv7180_write(state, ADV7180_REG_BRI, val);
552 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
555 ret = adv7180_write(state, ADV7180_REG_CON, val);
562 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
565 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
570 adv7180_write(state, 0x80d9, 0x44);
571 adv7180_write(state, ADV7180_REG_FLCONTROL,
575 adv7180_write(state, 0x80d9, 0xc4);
576 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
894 adv7180_write(state, ADV7180_REG_ICR3, isr3);
914 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
920 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
926 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
940 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
946 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
950 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
955 adv7180_write(state, 0x0080, 0x51);
956 adv7180_write(state, 0x0081, 0x51);
957 adv7180_write(state, 0x0082, 0x68);
962 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
963 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
964 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
967 adv7180_write(state,
971 adv7180_write(state,
974 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
975 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
978 adv7180_write(state, 0x0013, 0x00);
985 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
1047 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1052 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1053 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1061 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1064 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1074 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1078 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1079 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1080 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1081 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1082 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1084 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1085 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1086 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1087 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1088 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1267 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1283 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1289 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1293 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1298 ret = adv7180_write(state, ADV7180_REG_IMR3,
1303 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);